diff options
| author | Richard Lin | 2017-03-08 17:38:14 -0800 |
|---|---|---|
| committer | GitHub | 2017-03-08 17:38:14 -0800 |
| commit | a290d77ef3e88b200ab61cd41fcd1a1138321b66 (patch) | |
| tree | 3cbabf2a20dc34f9d60a585834f532070bcd5235 /src/main/scala/chisel3/util/Valid.scala | |
| parent | 09e95c484e145e2a1b2f0a1aacf549c7354a1eca (diff) | |
Deprecate old Reg with nulls constructor (#455)
Diffstat (limited to 'src/main/scala/chisel3/util/Valid.scala')
| -rw-r--r-- | src/main/scala/chisel3/util/Valid.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/chisel3/util/Valid.scala b/src/main/scala/chisel3/util/Valid.scala index 0bfe7cb3..000fff97 100644 --- a/src/main/scala/chisel3/util/Valid.scala +++ b/src/main/scala/chisel3/util/Valid.scala @@ -44,7 +44,7 @@ object Pipe out.bits <> enqBits out } else { - val v = Reg(Bool(), next=enqValid, init=false.B) + val v = RegNext(enqValid, false.B) val b = RegEnable(enqBits, enqValid) apply(v, b, latency-1) } |