Deprecate old Reg with nulls constructor (#455)

5 files changed, 11 insertions, 31 deletions

diff --git a/src/main/scala/chisel3/util/Counter.scala b/src/main/scala/chisel3/util/Counter.scala
index 6e533ea6..aa0c0d43 100644
--- a/src/main/scala/chisel3/util/Counter.scala
+++ b/src/main/scala/chisel3/util/Counter.scala
@@ -14,7 +14,7 @@ import chisel3.internal.naming.chiselName  // can't use chisel3_ version because
 @chiselName
 class Counter(val n: Int) {
   require(n >= 0)
-  val value = if (n > 1) Reg(init=0.U(log2Ceil(n).W)) else 0.U
+  val value = if (n > 1) RegInit(0.U(log2Ceil(n).W)) else 0.U
 
   /** Increment the counter, returning whether the counter currently is at the
     * maximum and will wrap. The incremented value is registered and will be
diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala
index 815a507b..67da6a17 100644
--- a/src/main/scala/chisel3/util/Decoupled.scala
+++ b/src/main/scala/chisel3/util/Decoupled.scala
@@ -182,7 +182,7 @@ extends Module(override_reset=override_reset) {
   private val ram = Mem(entries, gen)
   private val enq_ptr = Counter(entries)
   private val deq_ptr = Counter(entries)
-  private val maybe_full = Reg(init=false.B)
+  private val maybe_full = RegInit(false.B)
 
   private val ptr_match = enq_ptr.value === deq_ptr.value
   private val empty = ptr_match && !maybe_full
diff --git a/src/main/scala/chisel3/util/LFSR.scala b/src/main/scala/chisel3/util/LFSR.scala
index 94c340c4..ff2bf840 100644
--- a/src/main/scala/chisel3/util/LFSR.scala
+++ b/src/main/scala/chisel3/util/LFSR.scala
@@ -19,7 +19,7 @@ object LFSR16 {
   @chiselName
   def apply(increment: Bool = true.B): UInt = {
     val width = 16
-    val lfsr = Reg(init=1.U(width.W))
+    val lfsr = RegInit(1.U(width.W))
     when (increment) { lfsr := Cat(lfsr(0)^lfsr(2)^lfsr(3)^lfsr(5), lfsr(width-1,1)) }
     lfsr
   }
diff --git a/src/main/scala/chisel3/util/Reg.scala b/src/main/scala/chisel3/util/Reg.scala
index 27785dfb..e85a02fb 100644
--- a/src/main/scala/chisel3/util/Reg.scala
+++ b/src/main/scala/chisel3/util/Reg.scala
@@ -6,41 +6,21 @@ import chisel3._
 // TODO: remove this once we have CompileOptions threaded through the macro system.
 import chisel3.core.ExplicitCompileOptions.NotStrict
 
-object RegNext {
-  /** Returns a register with the specified next and no reset initialization.
-    *
-    * Essentially a 1-cycle delayed version of the input signal.
-    */
-  def apply[T <: Data](next: T): T = Reg[T](null.asInstanceOf[T], next, null.asInstanceOf[T])
-
-  /** Returns a register with the specified next and reset initialization.
-    *
-    * Essentially a 1-cycle delayed version of the input signal.
-    */
-  def apply[T <: Data](next: T, init: T): T = Reg[T](null.asInstanceOf[T], next, init)
-}
-
-object RegInit {
-  /** Returns a register pre-initialized (on reset) to the specified value.
-    */
-  def apply[T <: Data](init: T): T = Reg[T](null.asInstanceOf[T], null.asInstanceOf[T], init)
-}
-
 object RegEnable {
   /** Returns a register with the specified next, update enable gate, and no reset initialization.
     */
-  def apply[T <: Data](updateData: T, enable: Bool): T = {
-    val clonedUpdateData = updateData.chiselCloneType
-    val r = Reg(clonedUpdateData)
-    when (enable) { r := updateData }
+  def apply[T <: Data](next: T, enable: Bool): T = {
+    val clonedNext = next.chiselCloneType
+    val r = Reg(clonedNext)
+    when (enable) { r := next }
     r
   }
 
   /** Returns a register with the specified next, update enable gate, and reset initialization.
     */
-  def apply[T <: Data](updateData: T, resetData: T, enable: Bool): T = {
-    val r = RegInit(resetData)
-    when (enable) { r := updateData }
+  def apply[T <: Data](next: T, init: T, enable: Bool): T = {
+    val r = RegInit(init)
+    when (enable) { r := next }
     r
   }
 }
diff --git a/src/main/scala/chisel3/util/Valid.scala b/src/main/scala/chisel3/util/Valid.scala
index 0bfe7cb3..000fff97 100644
--- a/src/main/scala/chisel3/util/Valid.scala
+++ b/src/main/scala/chisel3/util/Valid.scala
@@ -44,7 +44,7 @@ object Pipe
       out.bits <> enqBits
       out
     } else {
-      val v = Reg(Bool(), next=enqValid, init=false.B)
+      val v = RegNext(enqValid, false.B)
       val b = RegEnable(enqBits, enqValid)
       apply(v, b, latency-1)
     }