diff options
| author | Jim Lawson | 2016-07-21 17:12:06 -0700 |
|---|---|---|
| committer | Jim Lawson | 2016-07-21 17:12:06 -0700 |
| commit | 7c9043859994b32bb07d2fce4ae61a7a3362a1b3 (patch) | |
| tree | 0f307e975393adf246e59aae0cc1b626e4ab4c7c /src/main/scala/chisel3/util/Reg.scala | |
| parent | d269818bdd4f2b71abebfaba9d7f8c9b4d488688 (diff) | |
Introduce chiselCloneType to distinguish from cloneType.
Still fails one test - DirectionSpec in Direction.scala
Diffstat (limited to 'src/main/scala/chisel3/util/Reg.scala')
| -rw-r--r-- | src/main/scala/chisel3/util/Reg.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/chisel3/util/Reg.scala b/src/main/scala/chisel3/util/Reg.scala index 81de4754..f77a9667 100644 --- a/src/main/scala/chisel3/util/Reg.scala +++ b/src/main/scala/chisel3/util/Reg.scala @@ -26,12 +26,12 @@ object RegEnable { def apply[T <: Data](updateData: T, enable: Bool): T = { val r = Reg(updateData) - when (enable) { r := updateData } + when (enable) { r := updateData.chiselCloneType } r } def apply[T <: Data](updateData: T, resetData: T, enable: Bool): T = { val r = RegInit(resetData) - when (enable) { r := updateData } + when (enable) { r := updateData.chiselCloneType } r } } |