diff options
| author | Jack Koenig | 2022-01-10 10:39:52 -0800 |
|---|---|---|
| committer | Jack Koenig | 2022-01-10 15:53:55 -0800 |
| commit | 3131c0daad41dea78bede4517669e376c41a325a (patch) | |
| tree | 55baed78a6a01f80ff3952a08233ca553a19964f /src/main/scala/chisel3/util/Reg.scala | |
| parent | dd36f97a82746cec0b25b94651581fe799e24579 (diff) | |
Apply scalafmt
Command:
sbt scalafmtAll
Diffstat (limited to 'src/main/scala/chisel3/util/Reg.scala')
| -rw-r--r-- | src/main/scala/chisel3/util/Reg.scala | 17 |
1 files changed, 8 insertions, 9 deletions
diff --git a/src/main/scala/chisel3/util/Reg.scala b/src/main/scala/chisel3/util/Reg.scala index e2b5d172..ddb74dd6 100644 --- a/src/main/scala/chisel3/util/Reg.scala +++ b/src/main/scala/chisel3/util/Reg.scala @@ -5,6 +5,7 @@ package chisel3.util import chisel3._ object RegEnable { + /** Returns a register with the specified next, update enable gate, and no reset initialization. * * @example {{{ @@ -13,7 +14,7 @@ object RegEnable { */ def apply[T <: Data](next: T, enable: Bool): T = { val r = Reg(chiselTypeOf(next)) - when (enable) { r := next } + when(enable) { r := next } r } @@ -25,13 +26,13 @@ object RegEnable { */ def apply[T <: Data](next: T, init: T, enable: Bool): T = { val r = RegInit(init) - when (enable) { r := next } + when(enable) { r := next } r } } -object ShiftRegister -{ +object ShiftRegister { + /** Returns the n-cycle delayed version of the input signal. * * @param in input to delay @@ -55,18 +56,17 @@ object ShiftRegister * val regDelayTwoReset = ShiftRegister(nextVal, 2, 0.U, ena) * }}} */ - def apply[T <: Data](in: T, n: Int, resetData: T, en: Bool): T = ShiftRegisters(in, n, resetData, en).lastOption.getOrElse(in) + def apply[T <: Data](in: T, n: Int, resetData: T, en: Bool): T = + ShiftRegisters(in, n, resetData, en).lastOption.getOrElse(in) } +object ShiftRegisters { -object ShiftRegisters -{ /** Returns a sequence of delayed input signal registers from 1 to n. * * @param in input to delay * @param n number of cycles to delay * @param en enable the shift - * */ def apply[T <: Data](in: T, n: Int, en: Bool = true.B): Seq[T] = Seq.iterate(in, n + 1)(util.RegEnable(_, en)).drop(1) @@ -77,7 +77,6 @@ object ShiftRegisters * @param n number of cycles to delay * @param resetData reset value for each register in the shift * @param en enable the shift - * */ def apply[T <: Data](in: T, n: Int, resetData: T, en: Bool): Seq[T] = Seq.iterate(in, n + 1)(util.RegEnable(_, resetData, en)).drop(1) |
