diff options
| author | Richard Lin | 2017-03-08 17:38:14 -0800 |
|---|---|---|
| committer | GitHub | 2017-03-08 17:38:14 -0800 |
| commit | a290d77ef3e88b200ab61cd41fcd1a1138321b66 (patch) | |
| tree | 3cbabf2a20dc34f9d60a585834f532070bcd5235 /src/main/scala/chisel3/util/Decoupled.scala | |
| parent | 09e95c484e145e2a1b2f0a1aacf549c7354a1eca (diff) | |
Deprecate old Reg with nulls constructor (#455)
Diffstat (limited to 'src/main/scala/chisel3/util/Decoupled.scala')
| -rw-r--r-- | src/main/scala/chisel3/util/Decoupled.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala index 815a507b..67da6a17 100644 --- a/src/main/scala/chisel3/util/Decoupled.scala +++ b/src/main/scala/chisel3/util/Decoupled.scala @@ -182,7 +182,7 @@ extends Module(override_reset=override_reset) { private val ram = Mem(entries, gen) private val enq_ptr = Counter(entries) private val deq_ptr = Counter(entries) - private val maybe_full = Reg(init=false.B) + private val maybe_full = RegInit(false.B) private val ptr_match = enq_ptr.value === deq_ptr.value private val empty = ptr_match && !maybe_full |