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authorducky2017-02-01 16:07:09 -0800
committerRichard Lin2017-02-07 16:24:17 -0800
commit8d2fff4eff3ba0f92437b290985b35afbb0ed565 (patch)
tree97b3f62d73c61ceb12ccb6bd684e63df5be8ed0d /src/main/scala/chisel3/util/CircuitMath.scala
parentad20406f301e04075e051147092cf9c12a6a6ca8 (diff)
Name all the things
Diffstat (limited to 'src/main/scala/chisel3/util/CircuitMath.scala')
-rw-r--r--src/main/scala/chisel3/util/CircuitMath.scala2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/main/scala/chisel3/util/CircuitMath.scala b/src/main/scala/chisel3/util/CircuitMath.scala
index b5f491ef..53d47694 100644
--- a/src/main/scala/chisel3/util/CircuitMath.scala
+++ b/src/main/scala/chisel3/util/CircuitMath.scala
@@ -6,6 +6,7 @@
package chisel3.util
import chisel3._
+import chisel3.internal.naming.chiselName // can't use chisel3_ version because of compile order
/** Returns the base-2 integer logarithm of an UInt.
*
@@ -21,6 +22,7 @@ import chisel3._
object Log2 {
/** Returns the base-2 integer logarithm of the least-significant `width` bits of an UInt.
*/
+ @chiselName
def apply(x: Bits, width: Int): UInt = {
if (width < 2) {
0.U