From 8d2fff4eff3ba0f92437b290985b35afbb0ed565 Mon Sep 17 00:00:00 2001
From: ducky
Date: Wed, 1 Feb 2017 16:07:09 -0800
Subject: Name all the things

---
 src/main/scala/chisel3/util/CircuitMath.scala | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'src/main/scala/chisel3/util/CircuitMath.scala')

diff --git a/src/main/scala/chisel3/util/CircuitMath.scala b/src/main/scala/chisel3/util/CircuitMath.scala
index b5f491ef..53d47694 100644
--- a/src/main/scala/chisel3/util/CircuitMath.scala
+++ b/src/main/scala/chisel3/util/CircuitMath.scala
@@ -6,6 +6,7 @@
 package chisel3.util
 
 import chisel3._
+import chisel3.internal.naming.chiselName  // can't use chisel3_ version because of compile order
 
 /** Returns the base-2 integer logarithm of an UInt.
   *
@@ -21,6 +22,7 @@ import chisel3._
 object Log2 {
   /** Returns the base-2 integer logarithm of the least-significant `width` bits of an UInt.
     */
+  @chiselName
   def apply(x: Bits, width: Int): UInt = {
     if (width < 2) {
       0.U
-- 
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