Apply scalafmt

Command:
sbt scalafmtAll

1 files changed, 5 insertions, 5 deletions

diff --git a/src/main/scala/chisel3/util/CircuitMath.scala b/src/main/scala/chisel3/util/CircuitMath.scala
index 58961630..df60f059 100644
--- a/src/main/scala/chisel3/util/CircuitMath.scala
+++ b/src/main/scala/chisel3/util/CircuitMath.scala
@@ -6,7 +6,7 @@
 package chisel3.util
 
 import chisel3._
-import chisel3.internal.naming.chiselName  // can't use chisel3_ version because of compile order
+import chisel3.internal.naming.chiselName // can't use chisel3_ version because of compile order
 
 /** Returns the base-2 integer logarithm of an UInt.
   *
@@ -17,9 +17,9 @@ import chisel3.internal.naming.chiselName  // can't use chisel3_ version because
   * Log2(13.U)  // evaluates to 3.U (truncation)
   * Log2(myUIntWire)
   * }}}
-  *
   */
 object Log2 {
+
   /** Returns the base-2 integer logarithm of the least-significant `width` bits of an UInt.
     */
   @chiselName
@@ -29,11 +29,11 @@ object Log2 {
     } else if (width == 2) {
       x(1)
     } else if (width <= divideAndConquerThreshold) {
-      Mux(x(width-1), (width-1).asUInt, apply(x, width-1))
+      Mux(x(width - 1), (width - 1).asUInt, apply(x, width - 1))
     } else {
       val mid = 1 << (log2Ceil(width) - 1)
-      val hi = x(width-1, mid)
-      val lo = x(mid-1, 0)
+      val hi = x(width - 1, mid)
+      val lo = x(mid - 1, 0)
       val useHi = hi.orR
       Cat(useHi, Mux(useHi, Log2(hi, width - mid), Log2(lo, mid)))
     }