diff options
| author | Jim Lawson | 2016-09-08 09:36:59 -0700 |
|---|---|---|
| committer | GitHub | 2016-09-08 09:36:59 -0700 |
| commit | b2ededb755c5b4d2ae182252142d97c6a126b6cf (patch) | |
| tree | 2f4316156af070bcb2d002c0245a9ef1daf0e03a /src/main/scala/chisel3/internal | |
| parent | 0ed5eb48cdb916b644aaf9e5dbf48f6cfb6c60f4 (diff) | |
| parent | f793453ba6c4c42ef61eda3af8f04f7cadf80b95 (diff) | |
Merge pull request #275 from ucb-bar/fix-printable
Fix bug in Printable FullName of submodule port
Diffstat (limited to 'src/main/scala/chisel3/internal')
| -rw-r--r-- | src/main/scala/chisel3/internal/firrtl/Emitter.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/chisel3/internal/firrtl/Emitter.scala b/src/main/scala/chisel3/internal/firrtl/Emitter.scala index 8ace27f9..8849077d 100644 --- a/src/main/scala/chisel3/internal/firrtl/Emitter.scala +++ b/src/main/scala/chisel3/internal/firrtl/Emitter.scala @@ -26,7 +26,7 @@ private class Emitter(circuit: Circuit) { case e: BulkConnect => s"${e.loc1.fullName(ctx)} <- ${e.loc2.fullName(ctx)}" case e: Stop => s"stop(${e.clk.fullName(ctx)}, UInt<1>(1), ${e.ret})" case e: Printf => - val (fmt, args) = e.pable.unpack + val (fmt, args) = e.pable.unpack(ctx) val printfArgs = Seq(e.clk.fullName(ctx), "UInt<1>(1)", "\"" + printf.format(fmt) + "\"") ++ args printfArgs mkString ("printf(", ", ", ")") |