diff options
| author | Jim Lawson | 2016-09-23 16:50:39 -0700 |
|---|---|---|
| committer | Jim Lawson | 2016-09-23 16:50:39 -0700 |
| commit | 3e174cc55be350a06e6e95ac6505a77167bd5a29 (patch) | |
| tree | 01813d93be83432a7c13fed6b1f56d9b9b942ca0 /src/main/scala/chisel3/internal | |
| parent | 9c88d767e04ac25ab72380c39f30e39c83abf563 (diff) | |
| parent | 785620b1403d827986bf60c2a001d8d6f71eed72 (diff) | |
Merge branch 'master' into gsdt
Diffstat (limited to 'src/main/scala/chisel3/internal')
| -rw-r--r-- | src/main/scala/chisel3/internal/firrtl/Emitter.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/chisel3/internal/firrtl/Emitter.scala b/src/main/scala/chisel3/internal/firrtl/Emitter.scala index 8849077d..f1908089 100644 --- a/src/main/scala/chisel3/internal/firrtl/Emitter.scala +++ b/src/main/scala/chisel3/internal/firrtl/Emitter.scala @@ -24,10 +24,10 @@ private class Emitter(circuit: Circuit) { case e: DefMemPort[_] => s"${e.dir} mport ${e.name} = ${e.source.fullName(ctx)}[${e.index.fullName(ctx)}], ${e.clock.fullName(ctx)}" case e: Connect => s"${e.loc.fullName(ctx)} <= ${e.exp.fullName(ctx)}" case e: BulkConnect => s"${e.loc1.fullName(ctx)} <- ${e.loc2.fullName(ctx)}" - case e: Stop => s"stop(${e.clk.fullName(ctx)}, UInt<1>(1), ${e.ret})" + case e: Stop => s"stop(${e.clock.fullName(ctx)}, UInt<1>(1), ${e.ret})" case e: Printf => val (fmt, args) = e.pable.unpack(ctx) - val printfArgs = Seq(e.clk.fullName(ctx), "UInt<1>(1)", + val printfArgs = Seq(e.clock.fullName(ctx), "UInt<1>(1)", "\"" + printf.format(fmt) + "\"") ++ args printfArgs mkString ("printf(", ", ", ")") case e: DefInvalid => s"${e.arg.fullName(ctx)} is invalid" |