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authorMartin Schoeberl2019-01-25 23:24:01 -0800
committerRichard Lin2019-01-25 23:24:01 -0800
commit5509cdd4c8332c53151e10ba5bdbe0684af1c05b (patch)
tree15f4a7e8f83e0d249918bbce4198160fb2c5360f /src/main/scala/chisel3/compatibility.scala
parent4f5ec211cb59f9da37dbe91d0dfcb93c4d3d84c9 (diff)
WireDefault instead of WireInit, keep WireInit around (#986)
Diffstat (limited to 'src/main/scala/chisel3/compatibility.scala')
-rw-r--r--src/main/scala/chisel3/compatibility.scala4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala
index 969a31eb..474058be 100644
--- a/src/main/scala/chisel3/compatibility.scala
+++ b/src/main/scala/chisel3/compatibility.scala
@@ -60,10 +60,10 @@ package object Chisel { // scalastyle:ignore package.object.name
import chisel3.core.CompileOptions
def apply[T <: Data](dummy: Int = 0, init: T)(implicit compileOptions: CompileOptions): T =
- chisel3.core.WireInit(init)
+ chisel3.core.WireDefault(init)
def apply[T <: Data](t: T, init: T)(implicit compileOptions: CompileOptions): T =
- chisel3.core.WireInit(t, init)
+ chisel3.core.WireDefault(t, init)
}
object Clock {
def apply(): Clock = new Clock