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| author | ducky | 2016-05-27 13:24:36 -0700 |
|---|---|---|
| committer | ducky | 2016-06-08 16:22:27 -0700 |
| commit | 881ac3cb3a9da0c7827a161238468df4727996f0 (patch) | |
| tree | 865b929b176ab1fd2c08fb4b7a083cdc2d132820 /src/main/scala/chisel/util/Valid.scala | |
| parent | 671117f3332ac10d1e7c5cc4f4cb5278f72ed6ab (diff) | |
Move utils into utils
Diffstat (limited to 'src/main/scala/chisel/util/Valid.scala')
| -rw-r--r-- | src/main/scala/chisel/util/Valid.scala | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/main/scala/chisel/util/Valid.scala b/src/main/scala/chisel/util/Valid.scala index cffed0a7..56ac9abb 100644 --- a/src/main/scala/chisel/util/Valid.scala +++ b/src/main/scala/chisel/util/Valid.scala @@ -3,7 +3,9 @@ /** Wrappers for valid interfaces and associated circuit generators using them. */ -package chisel +package chisel.util + +import chisel._ /** An I/O Bundle containing data and a signal determining if it is valid */ class ValidIO[+T <: Data](gen2: T) extends Bundle |