diff options
| author | Jim Lawson | 2016-03-14 11:10:36 -0700 |
|---|---|---|
| committer | Jim Lawson | 2016-03-14 11:10:36 -0700 |
| commit | 541b2d4cb0b3e01d22f442b4cae7dcc6f910af41 (patch) | |
| tree | 9ded3b0ad45f78d0b47e5e6b9419a8a0f3b2165e /src/main/scala/Chisel/Mem.scala | |
| parent | 62794befadd8477af26919e453d4bdbbad83dd1f (diff) | |
Scalastyle cleanup - no functional differences.
Diffstat (limited to 'src/main/scala/Chisel/Mem.scala')
| -rw-r--r-- | src/main/scala/Chisel/Mem.scala | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/main/scala/Chisel/Mem.scala b/src/main/scala/Chisel/Mem.scala index 21284607..17ac9ca5 100644 --- a/src/main/scala/Chisel/Mem.scala +++ b/src/main/scala/Chisel/Mem.scala @@ -62,10 +62,12 @@ sealed abstract class MemBase[T <: Data](t: T, val length: Int) extends HasId wi def write(idx: UInt, data: T, mask: Vec[Bool]) (implicit evidence: T <:< Vec[_]): Unit = { val accessor = makePort(idx, MemPortDirection.WRITE).asInstanceOf[Vec[Data]] val dataVec = data.asInstanceOf[Vec[Data]] - if (accessor.length != dataVec.length) + if (accessor.length != dataVec.length) { Builder.error(s"Mem write data must contain ${accessor.length} elements (found ${dataVec.length})") - if (accessor.length != mask.length) + } + if (accessor.length != mask.length) { Builder.error(s"Mem write mask must contain ${accessor.length} elements (found ${mask.length})") + } for (((cond, port), datum) <- mask zip accessor zip dataVec) when (cond) { port := datum } } |
