Scalastyle cleanup - no functional differences.

6 files changed, 25 insertions, 16 deletions

diff --git a/src/main/scala/Chisel/Driver.scala b/src/main/scala/Chisel/Driver.scala
index ca77eb33..d96787d1 100644
--- a/src/main/scala/Chisel/Driver.scala
+++ b/src/main/scala/Chisel/Driver.scala
@@ -122,8 +122,9 @@ object Driver extends BackendCompilationUtilities {
   private var target_dir: Option[String] = None
   def parseArgs(args: Array[String]): Unit = {
     for (i <- 0 until args.size) {
-      if (args(i) == "--targetDir")
-        target_dir = Some(args(i+1))
+      if (args(i) == "--targetDir") {
+        target_dir = Some(args(i + 1))
+      }
     }
   }
 
diff --git a/src/main/scala/Chisel/FileSystemUtilities.scala b/src/main/scala/Chisel/FileSystemUtilities.scala
index efb7178d..575ae138 100644
--- a/src/main/scala/Chisel/FileSystemUtilities.scala
+++ b/src/main/scala/Chisel/FileSystemUtilities.scala
@@ -1,10 +1,10 @@
-// See LICENSE for details
+// See LICENSE for license details.
 
 package Chisel
 
 @deprecated("FileSystemUtilities doesn't exist in chisel3", "3.0.0")
 trait FileSystemUtilities {
-  def createOutputFile(name: String) = {
+  def createOutputFile(name: String): java.io.FileWriter  = {
     new java.io.FileWriter(Driver.targetDir + "/" + name)
   }
 }
diff --git a/src/main/scala/Chisel/Main.scala b/src/main/scala/Chisel/Main.scala
index 349f8b18..0151a288 100644
--- a/src/main/scala/Chisel/Main.scala
+++ b/src/main/scala/Chisel/Main.scala
@@ -1,14 +1,14 @@
-// See LICENSE for details
+// See LICENSE for license details.
 
 package Chisel
 
 import java.io.File
 
 @deprecated("chiselMain doesn't exist in Chisel3", "3.0") object chiselMain {
-  def apply[T <: Module](args: Array[String], gen: () => T) =
+  def apply[T <: Module](args: Array[String], gen: () => T): Unit =
     Predef.assert(false)
 
-  def run[T <: Module] (args: Array[String], gen: () => T) = {
+  def run[T <: Module] (args: Array[String], gen: () => T): Unit = {
     def circuit = Driver.elaborate(gen)
     def output_file = new File(Driver.targetDir + "/" + circuit.name + ".fir")
     Driver.parseArgs(args)
diff --git a/src/main/scala/Chisel/Mem.scala b/src/main/scala/Chisel/Mem.scala
index 21284607..17ac9ca5 100644
--- a/src/main/scala/Chisel/Mem.scala
+++ b/src/main/scala/Chisel/Mem.scala
@@ -62,10 +62,12 @@ sealed abstract class MemBase[T <: Data](t: T, val length: Int) extends HasId wi
   def write(idx: UInt, data: T, mask: Vec[Bool]) (implicit evidence: T <:< Vec[_]): Unit = {
     val accessor = makePort(idx, MemPortDirection.WRITE).asInstanceOf[Vec[Data]]
     val dataVec = data.asInstanceOf[Vec[Data]]
-    if (accessor.length != dataVec.length)
+    if (accessor.length != dataVec.length) {
       Builder.error(s"Mem write data must contain ${accessor.length} elements (found ${dataVec.length})")
-    if (accessor.length != mask.length)
+    }
+    if (accessor.length != mask.length) {
       Builder.error(s"Mem write mask must contain ${accessor.length} elements (found ${mask.length})")
+    }
     for (((cond, port), datum) <- mask zip accessor zip dataVec)
       when (cond) { port := datum }
   }
diff --git a/src/main/scala/Chisel/internal/firrtl/IR.scala b/src/main/scala/Chisel/internal/firrtl/IR.scala
index d53807c6..8a937419 100644
--- a/src/main/scala/Chisel/internal/firrtl/IR.scala
+++ b/src/main/scala/Chisel/internal/firrtl/IR.scala
@@ -57,7 +57,8 @@ abstract class LitArg(val num: BigInt, widthArg: Width) extends Arg {
 
   protected def minWidth: Int
   if (forcedWidth) {
-    require(widthArg.get >= minWidth, s"The literal value ${num} was elaborated with a specificed width of ${widthArg.get} bits, but at least ${minWidth} bits are required.")
+    require(widthArg.get >= minWidth,
+      s"The literal value ${num} was elaborated with a specificed width of ${widthArg.get} bits, but at least ${minWidth} bits are required.")
   }
 }
 
@@ -165,12 +166,17 @@ case class Component(id: Module, name: String, ports: Seq[Port], commands: Seq[C
 case class Port(id: Data, dir: Direction)
 case class Printf(clk: Arg, formatIn: String, ids: Seq[Arg]) extends Command {
   require(formatIn.forall(c => c.toInt > 0 && c.toInt < 128), "format strings must comprise non-null ASCII values")
-  def format = {
+  def format: String = {
     def escaped(x: Char) =
-      if (x == '"' || x == '\\' || x == '?') "\\" + x
-      else if (x == '\n') "\\n"
-      else if (x.toInt < 32) s"\\x${BigInt(x.toInt).toString(16)}"
-      else x
+      if (x == '"' || x == '\\' || x == '?') {
+        "\\" + x
+      } else if (x == '\n') {
+        "\\n"
+      } else if (x.toInt < 32) {
+        s"\\x${BigInt(x.toInt).toString(16)}"
+      } else {
+        x
+      }
     formatIn.map(escaped _).mkString
   }
 }
diff --git a/src/main/scala/Chisel/throwException.scala b/src/main/scala/Chisel/throwException.scala
index 998b2cd6..1932bec8 100644
--- a/src/main/scala/Chisel/throwException.scala
+++ b/src/main/scala/Chisel/throwException.scala
@@ -1,4 +1,4 @@
-// See LICENSE for details
+// See LICENSE for license details.
 
 package Chisel