Fix val io = new Bundle{...}.flip

Now, we emit all I/Os inside a bundle named io.

1 files changed, 3 insertions, 3 deletions

diff --git a/src/main/scala/Chisel/IR.scala b/src/main/scala/Chisel/IR.scala
index 90ca349c..8b642902 100644
--- a/src/main/scala/Chisel/IR.scala
+++ b/src/main/scala/Chisel/IR.scala
@@ -82,9 +82,9 @@ case class SLit(n: BigInt, w: Width) extends LitArg(n, w) {
 }
 
 case class Ref(name: String) extends Immediate
-case class ModuleIO(mod: Module) extends Immediate {
-  def name = mod.getRef.name
-  override def fullName(ctx: Component) = if (mod eq ctx.id) "" else name
+case class ModuleIO(mod: Module, name: String) extends Immediate {
+  override def fullName(ctx: Component) =
+    if (mod eq ctx.id) name else s"${mod.getRef.name}.$name"
 }
 case class Slot(imm: Alias, name: String) extends Immediate {
   override def fullName(ctx: Component) =