Fix val io = new Bundle{...}.flip

Now, we emit all I/Os inside a bundle named io.

2 files changed, 14 insertions, 18 deletions

diff --git a/src/main/scala/Chisel/Core.scala b/src/main/scala/Chisel/Core.scala
index 8f1b6b14..742878be 100644
--- a/src/main/scala/Chisel/Core.scala
+++ b/src/main/scala/Chisel/Core.scala
@@ -801,9 +801,11 @@ abstract class Module(_clock: Clock = null, _reset: Bool = null) extends HasId {
   private[Chisel] def ref = Builder.globalRefMap(this)
   private[Chisel] def lref = ref
 
-  private[Chisel] def computePorts = io.namedElts.unzip._2 map { x =>
-    val bundleDir = if (io.isFlip ^ x.isFlip) INPUT else OUTPUT
-    Port(x, if (x.dir == NO_DIR) bundleDir else x.dir)
+  private def ports = (clock, "clock") :: (reset, "reset") :: (io, "io") :: Nil
+
+  private[Chisel] def computePorts = ports map { case (port, name) =>
+    val bundleDir = if (port.isFlip) INPUT else OUTPUT
+    Port(port, if (port.dir == NO_DIR) bundleDir else port.dir)
   }
 
   private def connectImplicitIOs(): this.type = _parent match {
@@ -814,30 +816,24 @@ abstract class Module(_clock: Clock = null, _reset: Bool = null) extends HasId {
     case None => this
   }
 
-  private def makeImplicitIOs(): this.type  = {
-    io.addElt("clock", clock)
-    io.addElt("reset", reset)
-    this
+  private def makeImplicitIOs(): Unit = ports map { case (port, name) =>
   }
 
   private def setRefs(): this.type = {
+    for ((port, name) <- ports)
+      port.setRef(ModuleIO(this, _namespace.name(name)))
+
     val valNames = HashSet[String](getClass.getDeclaredFields.map(_.getName):_*)
     def isPublicVal(m: java.lang.reflect.Method) =
       m.getParameterTypes.isEmpty && valNames.contains(m.getName)
-
-    makeImplicitIOs
-    _ids.foreach(_._onModuleClose)
-
-    // FIRRTL: the IO namespace is part of the module namespace
-    io.setRef(ModuleIO(this))
-    for((name, elt) <- io.namedElts) { _namespace.name(name) }
-
     val methods = getClass.getMethods.sortWith(_.getName > _.getName)
     for (m <- methods; if isPublicVal(m)) m.invoke(this) match {
       case id: HasId => id.setRef(_namespace.name(m.getName))
       case _ =>
     }
+
     _ids.foreach(_.setRef(_namespace.name("T")))
+    _ids.foreach(_._onModuleClose)
     this
   }
 
diff --git a/src/main/scala/Chisel/IR.scala b/src/main/scala/Chisel/IR.scala
index 90ca349c..8b642902 100644
--- a/src/main/scala/Chisel/IR.scala
+++ b/src/main/scala/Chisel/IR.scala
@@ -82,9 +82,9 @@ case class SLit(n: BigInt, w: Width) extends LitArg(n, w) {
 }
 
 case class Ref(name: String) extends Immediate
-case class ModuleIO(mod: Module) extends Immediate {
-  def name = mod.getRef.name
-  override def fullName(ctx: Component) = if (mod eq ctx.id) "" else name
+case class ModuleIO(mod: Module, name: String) extends Immediate {
+  override def fullName(ctx: Component) =
+    if (mod eq ctx.id) name else s"${mod.getRef.name}.$name"
 }
 case class Slot(imm: Alias, name: String) extends Immediate {
   override def fullName(ctx: Component) =