diff options
| author | Andrew Waterman | 2015-08-26 14:57:55 -0700 |
|---|---|---|
| committer | Andrew Waterman | 2015-08-26 15:21:46 -0700 |
| commit | 794a1230e61a9a358fcb852fca3b84cab237dcf9 (patch) | |
| tree | 119180a27685a781f844b6008245f3f56d75ff82 /src/main/scala/Chisel/IR.scala | |
| parent | a3af1ac0f11daf9d2f7a29a2f57b0fa99d81b277 (diff) | |
Remove Mem from Data hierarchy
Just like Reg, state elements are not Data.
Diffstat (limited to 'src/main/scala/Chisel/IR.scala')
| -rw-r--r-- | src/main/scala/Chisel/IR.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/Chisel/IR.scala b/src/main/scala/Chisel/IR.scala index 292dc820..97c4ff15 100644 --- a/src/main/scala/Chisel/IR.scala +++ b/src/main/scala/Chisel/IR.scala @@ -141,7 +141,7 @@ abstract class Definition extends Command { case class DefPrim[T <: Data](id: T, op: PrimOp, args: Arg*) extends Definition case class DefWire(id: Data) extends Definition case class DefRegister(id: Data, clock: Arg, reset: Arg) extends Definition -case class DefMemory(id: Data, size: Int, clock: Arg) extends Definition +case class DefMemory(id: HasId, t: Data, size: Int, clock: Arg) extends Definition case class DefSeqMemory(id: Data, size: Int) extends Definition case class DefAccessor(id: HasId, source: Alias, direction: Direction, index: Arg) extends Definition case class DefInstance(id: Module, ports: Seq[Data]) extends Definition |