Remove Mem from Data hierarchy

Just like Reg, state elements are not Data.

3 files changed, 4 insertions, 8 deletions

diff --git a/src/main/scala/Chisel/Core.scala b/src/main/scala/Chisel/Core.scala
index 9500de69..987569e9 100644
--- a/src/main/scala/Chisel/Core.scala
+++ b/src/main/scala/Chisel/Core.scala
@@ -137,12 +137,12 @@ object Mem {
   def apply[T <: Data](t: T, size: Int): Mem[T] = {
     val mt  = t.cloneType
     val mem = new Mem(mt, size)
-    pushCommand(DefMemory(mem, size, Alias(mt._parent.get.clock))) // TODO multi-clock
+    pushCommand(DefMemory(mem, mt, size, Alias(mt._parent.get.clock))) // TODO multi-clock
     mem
   }
 }
 
-sealed class Mem[T <: Data](t: T, val length: Int) extends Aggregate(NO_DIR) with VecLike[T] {
+sealed class Mem[T <: Data](t: T, val length: Int) extends HasId with VecLike[T] {
   def apply(idx: Int): T = apply(UInt(idx))
   def apply(idx: UInt): T = {
     val x = t.cloneType
@@ -157,10 +157,6 @@ sealed class Mem[T <: Data](t: T, val length: Int) extends Aggregate(NO_DIR) wit
     val mask1 = mask.toBits
     write(idx, t.fromBits((read(idx).toBits & ~mask1) | (data.toBits & mask1)))
   }
-
-  def cloneType = throwException("Mem.cloneType unimplemented")
-  private[Chisel] def flatten = throwException("Mem.flatten unimplemented")
-  private[Chisel] def toType = t.toType
 }
 
 object SeqMem {
diff --git a/src/main/scala/Chisel/Emitter.scala b/src/main/scala/Chisel/Emitter.scala
index fd271aa4..867b2107 100644
--- a/src/main/scala/Chisel/Emitter.scala
+++ b/src/main/scala/Chisel/Emitter.scala
@@ -11,7 +11,7 @@ private class Emitter(circuit: Circuit) {
     case e: DefPrim[_] => s"node ${e.name} = ${e.op.name}(${e.args.map(_.fullName(ctx)).reduce(_+", "+_)})"
     case e: DefWire => s"wire ${e.name} : ${e.id.toType}"
     case e: DefRegister => s"reg ${e.name} : ${e.id.toType}, ${e.clock.fullName(ctx)}, ${e.reset.fullName(ctx)}"
-    case e: DefMemory => s"cmem ${e.name} : ${e.id.toType}[${e.size}], ${e.clock.fullName(ctx)}";
+    case e: DefMemory => s"cmem ${e.name} : ${e.t.toType}[${e.size}], ${e.clock.fullName(ctx)}"
     case e: DefSeqMemory => s"smem ${e.name} : ${e.id.toType}[${e.size}]";
     case e: DefAccessor => s"infer accessor ${e.name} = ${e.source.fullName(ctx)}[${e.index.fullName(ctx)}]"
     case e: Connect => s"${e.loc.fullName(ctx)} := ${e.exp.fullName(ctx)}"
diff --git a/src/main/scala/Chisel/IR.scala b/src/main/scala/Chisel/IR.scala
index 292dc820..97c4ff15 100644
--- a/src/main/scala/Chisel/IR.scala
+++ b/src/main/scala/Chisel/IR.scala
@@ -141,7 +141,7 @@ abstract class Definition extends Command {
 case class DefPrim[T <: Data](id: T, op: PrimOp, args: Arg*) extends Definition
 case class DefWire(id: Data) extends Definition
 case class DefRegister(id: Data, clock: Arg, reset: Arg) extends Definition
-case class DefMemory(id: Data, size: Int, clock: Arg) extends Definition
+case class DefMemory(id: HasId, t: Data, size: Int, clock: Arg) extends Definition
 case class DefSeqMemory(id: Data, size: Int) extends Definition
 case class DefAccessor(id: HasId, source: Alias, direction: Direction, index: Arg) extends Definition
 case class DefInstance(id: Module, ports: Seq[Data]) extends Definition