diff options
| author | Andrew Waterman | 2015-08-27 17:06:49 -0700 |
|---|---|---|
| committer | Andrew Waterman | 2015-08-27 23:43:26 -0700 |
| commit | 5293b1cfdcc18a4879f476a1c0370ec19e409089 (patch) | |
| tree | d5e6ba926bb33cab297ddd87734725090324c779 /src/main/scala/Chisel/IR.scala | |
| parent | 6ab5d0c440d77fa84b9ca2aab7b209b4f3108b0c (diff) | |
Fix bug where flipping top-level I/O had no effect
The fix is to propagate the flip to the fields in the bundle.
Diffstat (limited to 'src/main/scala/Chisel/IR.scala')
| -rw-r--r-- | src/main/scala/Chisel/IR.scala | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/main/scala/Chisel/IR.scala b/src/main/scala/Chisel/IR.scala index 97c4ff15..209e9f64 100644 --- a/src/main/scala/Chisel/IR.scala +++ b/src/main/scala/Chisel/IR.scala @@ -144,14 +144,15 @@ case class DefRegister(id: Data, clock: Arg, reset: Arg) extends Definition case class DefMemory(id: HasId, t: Data, size: Int, clock: Arg) extends Definition case class DefSeqMemory(id: Data, size: Int) extends Definition case class DefAccessor(id: HasId, source: Alias, direction: Direction, index: Arg) extends Definition -case class DefInstance(id: Module, ports: Seq[Data]) extends Definition +case class DefInstance(id: Module, ports: Seq[Port]) extends Definition case class WhenBegin(pred: Arg) extends Command case class WhenElse() extends Command case class WhenEnd() extends Command case class Connect(loc: Alias, exp: Arg) extends Command case class BulkConnect(loc1: Alias, loc2: Alias) extends Command case class ConnectInit(loc: Alias, exp: Arg) extends Command -case class Component(id: Module, name: String, ports: Seq[Data], commands: Seq[Command]) extends Immediate +case class Component(id: Module, name: String, ports: Seq[Port], commands: Seq[Command]) extends Immediate +case class Port(id: Data, dir: Direction) case class Circuit(name: String, components: Seq[Component], refMap: RefMap, parameterDump: ParameterDump) { def emit = new Emitter(this).toString |