Fix bug where flipping top-level I/O had no effect

The fix is to propagate the flip to the fields in the bundle.

1 files changed, 2 insertions, 4 deletions

diff --git a/src/main/scala/Chisel/Emitter.scala b/src/main/scala/Chisel/Emitter.scala
index 867b2107..80c6adf0 100644
--- a/src/main/scala/Chisel/Emitter.scala
+++ b/src/main/scala/Chisel/Emitter.scala
@@ -3,10 +3,8 @@ package Chisel
 private class Emitter(circuit: Circuit) {
   override def toString = res.toString
 
-  private def emitPort(e: Data): String = {
-    val dir = if (e.isFlip) "input" else "output"
-    s"$dir ${e.getRef.name} : ${e.toType}"
-  }
+  private def emitPort(e: Port): String =
+    s"${e.dir} ${e.id.getRef.name} : ${e.id.toType}"
   private def emit(e: Command, ctx: Component): String = e match {
     case e: DefPrim[_] => s"node ${e.name} = ${e.op.name}(${e.args.map(_.fullName(ctx)).reduce(_+", "+_)})"
     case e: DefWire => s"wire ${e.name} : ${e.id.toType}"