Extend TesterDriver to optionally take in additional Verilog sources

1 files changed, 21 insertions, 9 deletions

diff --git a/src/main/scala/Chisel/Driver.scala b/src/main/scala/Chisel/Driver.scala
index a31786d9..b57653c3 100644
--- a/src/main/scala/Chisel/Driver.scala
+++ b/src/main/scala/Chisel/Driver.scala
@@ -46,22 +46,34 @@ trait BackendCompilationUtilities {
       dir)
   }
 
+  /** Generates a Verilator invocation to convert Verilog sources to C++
+    * simulation sources.
+    *
+    * @param prefix output class name
+    * @param dir output directory
+    * @oaran vDut .v file containing the top-level DUR
+    * @param vSources list of additional Verilog sources to compile
+    * @param cppHarness C++ testharness to compile/link against
+    * @param vH .h file to generate
+    */
   def verilogToCpp(
       prefix: String,
       dir: File,
       vDut: File,
+      vSources: Seq[File],
       cppHarness: File,
       vH: File): ProcessBuilder =
     Seq("verilator",
-        "--cc", vDut.toString,
-        "--assert",
-        "--Wno-fatal",
-        "--trace",
-        "-O2",
-        "+define+TOP_TYPE=V" + prefix,
-        "-CFLAGS", s"""-Wno-undefined-bool-conversion -O2 -DTOP_TYPE=V$prefix -include ${vH.toString}""",
-        "-Mdir", dir.toString,
-        "--exe", cppHarness.toString)
+        "--cc", vDut.toString) ++
+        vSources.map(file => Seq("-v", file.toString)).flatten ++
+        Seq("--assert",
+            "--Wno-fatal",
+            "--trace",
+            "-O2",
+            "+define+TOP_TYPE=V" + prefix,
+            "-CFLAGS", s"""-Wno-undefined-bool-conversion -O2 -DTOP_TYPE=V$prefix -include ${vH.toString}""",
+            "-Mdir", dir.toString,
+            "--exe", cppHarness.toString)
 
   def cppToExe(prefix: String, dir: File): ProcessBuilder =
     Seq("make", "-C", dir.toString, "-j", "-f", s"V${prefix}.mk", s"V${prefix}")