diff options
| author | Andrew Waterman | 2015-09-18 13:29:16 -0700 |
|---|---|---|
| committer | Andrew Waterman | 2015-09-18 13:29:16 -0700 |
| commit | f71b738e657ad783fa776a27b864eb93d55faa53 (patch) | |
| tree | 8efe409b3a414acf4cbbe70fecd6f50f6f60435f /src/main/scala/Chisel/Core.scala | |
| parent | 3d7a3b9da122df6f04a1c3ef10ec7de7eaa5e8a7 (diff) | |
Use FIRRTL idiom for SeqMem read-enables
Emit read-enables as mux(ren, addr, poison).
Diffstat (limited to 'src/main/scala/Chisel/Core.scala')
| -rw-r--r-- | src/main/scala/Chisel/Core.scala | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/main/scala/Chisel/Core.scala b/src/main/scala/Chisel/Core.scala index 5565e87e..74f07756 100644 --- a/src/main/scala/Chisel/Core.scala +++ b/src/main/scala/Chisel/Core.scala @@ -168,7 +168,8 @@ object SeqMem { } sealed class SeqMem[T <: Data](t: T, n: Int) extends MemBase[T](t, n) { - def read(addr: UInt, enable: Bool): T = read(addr) // TODO read enable + def read(addr: UInt, enable: Bool): T = + read(Mux(enable, addr, Poison(addr))) } object Vec { |