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-rw-r--r--src/main/scala/Chisel/Core.scala3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/main/scala/Chisel/Core.scala b/src/main/scala/Chisel/Core.scala
index 5565e87e..74f07756 100644
--- a/src/main/scala/Chisel/Core.scala
+++ b/src/main/scala/Chisel/Core.scala
@@ -168,7 +168,8 @@ object SeqMem {
}
sealed class SeqMem[T <: Data](t: T, n: Int) extends MemBase[T](t, n) {
- def read(addr: UInt, enable: Bool): T = read(addr) // TODO read enable
+ def read(addr: UInt, enable: Bool): T =
+ read(Mux(enable, addr, Poison(addr)))
}
object Vec {