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authorAndrew Waterman2015-08-20 23:26:04 -0700
committerAndrew Waterman2015-08-26 15:21:45 -0700
commit834dd38ea1bc6c6ac5453d8e73893910a5dcc968 (patch)
treedfc4c56ff4f5a861b01233e89ae2450e4c4c6c97 /src/main/scala/Chisel/Core.scala
parentd2e3c20eff2f8098a9b5b96bc81d5e32e202b69e (diff)
Simplify I/O zero-initialization
Diffstat (limited to 'src/main/scala/Chisel/Core.scala')
-rw-r--r--src/main/scala/Chisel/Core.scala6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/main/scala/Chisel/Core.scala b/src/main/scala/Chisel/Core.scala
index 60b22830..8495a5d4 100644
--- a/src/main/scala/Chisel/Core.scala
+++ b/src/main/scala/Chisel/Core.scala
@@ -781,10 +781,16 @@ object Module {
paramsScope(currParams) {
val parent = dynamicContext.currentModule
val m = bc.setRefs()
+ // init module outputs
+ m._commands prependAll (for (p <- m.io.flatten; if p.dir == OUTPUT)
+ yield Connect(p.lref, p.fromInt(0).ref))
dynamicContext.currentModule = parent
val ports = m.computePorts
Builder.components += Component(m, m.name, ports, m._commands)
pushCommand(DefInstance(m, ports))
+ // init instance inputs
+ for (p <- m.io.flatten; if p.dir == INPUT)
+ p := p.fromInt(0)
m
}.connectImplicitIOs()
}