From 834dd38ea1bc6c6ac5453d8e73893910a5dcc968 Mon Sep 17 00:00:00 2001
From: Andrew Waterman
Date: Thu, 20 Aug 2015 23:26:04 -0700
Subject: Simplify I/O zero-initialization

---
 src/main/scala/Chisel/Core.scala | 6 ++++++
 1 file changed, 6 insertions(+)

(limited to 'src/main/scala/Chisel/Core.scala')

diff --git a/src/main/scala/Chisel/Core.scala b/src/main/scala/Chisel/Core.scala
index 60b22830..8495a5d4 100644
--- a/src/main/scala/Chisel/Core.scala
+++ b/src/main/scala/Chisel/Core.scala
@@ -781,10 +781,16 @@ object Module {
     paramsScope(currParams) {
       val parent = dynamicContext.currentModule
       val m = bc.setRefs()
+      // init module outputs
+      m._commands prependAll (for (p <- m.io.flatten; if p.dir == OUTPUT)
+        yield Connect(p.lref, p.fromInt(0).ref))
       dynamicContext.currentModule = parent
       val ports = m.computePorts
       Builder.components += Component(m, m.name, ports, m._commands)
       pushCommand(DefInstance(m, ports))
+      // init instance inputs
+      for (p <- m.io.flatten; if p.dir == INPUT)
+        p := p.fromInt(0)
       m
     }.connectImplicitIOs()
   }
-- 
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