diff options
| author | ducky | 2015-10-30 14:53:17 -0700 |
|---|---|---|
| committer | ducky | 2015-10-30 14:53:17 -0700 |
| commit | 78dd6b801f0988c381f47c76ca23b58f17eee942 (patch) | |
| tree | 433a8b174c1410a209cdf185676adca9fa559169 /src/main/scala/Chisel/Bits.scala | |
| parent | 22127c79c872ebcf5da50858c7309ad82d39eb63 (diff) | |
Move Cat into utils
Diffstat (limited to 'src/main/scala/Chisel/Bits.scala')
| -rw-r--r-- | src/main/scala/Chisel/Bits.scala | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/main/scala/Chisel/Bits.scala b/src/main/scala/Chisel/Bits.scala index 209dbd1f..021532a1 100644 --- a/src/main/scala/Chisel/Bits.scala +++ b/src/main/scala/Chisel/Bits.scala @@ -175,7 +175,10 @@ sealed abstract class Bits(dirArg: Direction, width: Width, override val litArg: * * The width of the output is sum of the inputs. Generates no logic. */ - def ## (other: Bits): UInt = Cat(this, other) + def ## (other: Bits): UInt = { + val w = this.width + other.width + pushOp(DefPrim(UInt(w), ConcatOp, this.ref, other.ref)) + } @deprecated("Use asBits, which makes the reinterpret cast more explicit and actually returns Bits", "chisel3") override def toBits: UInt = asUInt |
