diff options
| author | Andrew Waterman | 2016-04-05 15:19:42 -0700 |
|---|---|---|
| committer | Andrew Waterman | 2016-04-05 16:09:48 -0700 |
| commit | f9689cab3bbb5cb2cddbb429bc30d630c886034d (patch) | |
| tree | 7f6f6f06327ca346f1d7a5189d0aea0290615d31 /src/main/scala/Chisel/Aggregate.scala | |
| parent | 5d6547ad929730223fbcdeb7bf8fefbf8deba2bb (diff) | |
Make Wire(init = x) behave the same as Wire(t = x) := x
There's a separate debate to be had about whether we want to
default-initialize Wires to invalid. This patch just fixes the
implementation of the previous, unsafe approach, which was usually,
but not always, defaulting to invalid.
Diffstat (limited to 'src/main/scala/Chisel/Aggregate.scala')
| -rw-r--r-- | src/main/scala/Chisel/Aggregate.scala | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/main/scala/Chisel/Aggregate.scala b/src/main/scala/Chisel/Aggregate.scala index 3df48052..6bf656a9 100644 --- a/src/main/scala/Chisel/Aggregate.scala +++ b/src/main/scala/Chisel/Aggregate.scala @@ -46,8 +46,7 @@ object Vec { require(!elts.isEmpty) val width = elts.map(_.width).reduce(_ max _) - val vec = new Vec(elts.head.cloneTypeWidth(width), elts.length) - pushCommand(DefWire(vec)) + val vec = Wire(new Vec(elts.head.cloneTypeWidth(width), elts.length)) for ((v, e) <- vec zip elts) v := e vec |