diff options
| author | Jiuyang Liu | 2021-12-15 15:53:52 +0800 |
|---|---|---|
| committer | GitHub | 2021-12-15 07:53:52 +0000 |
| commit | 36506c527ff0f51636beee4160f0ce1f6ad2f90a (patch) | |
| tree | ef6f708959d6f115154d76ddd6216a7ba288a01f /integration-tests/src/test/scala/chiselTests/util/experimental/DecoderSpec.scala | |
| parent | 7e8ec50376f852d5ab35d7609d986c7e4128abb1 (diff) | |
Refactor TruthTable to use Seq (#2217)
This makes the resulting Verilog from decoding a TruthTable deterministic.
Diffstat (limited to 'integration-tests/src/test/scala/chiselTests/util/experimental/DecoderSpec.scala')
| -rw-r--r-- | integration-tests/src/test/scala/chiselTests/util/experimental/DecoderSpec.scala | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/integration-tests/src/test/scala/chiselTests/util/experimental/DecoderSpec.scala b/integration-tests/src/test/scala/chiselTests/util/experimental/DecoderSpec.scala index c31fdee0..2d50555e 100644 --- a/integration-tests/src/test/scala/chiselTests/util/experimental/DecoderSpec.scala +++ b/integration-tests/src/test/scala/chiselTests/util/experimental/DecoderSpec.scala @@ -10,7 +10,7 @@ import chiseltest._ import chiseltest.formal._ class DecoderSpec extends AnyFlatSpec with ChiselScalatestTester with Formal { - val xor = TruthTable( + val xor = TruthTable.fromString( """10->1 |01->1 | 0""".stripMargin) @@ -42,7 +42,7 @@ class DecoderSpec extends AnyFlatSpec with ChiselScalatestTester with Formal { """10->1 |01->1 | 0""".stripMargin, - QMCMinimizer.minimize(TruthTable( + QMCMinimizer.minimize(TruthTable.fromString( """10->1 |01->1 | 0""".stripMargin)).toString |