From 36506c527ff0f51636beee4160f0ce1f6ad2f90a Mon Sep 17 00:00:00 2001
From: Jiuyang Liu
Date: Wed, 15 Dec 2021 15:53:52 +0800
Subject: Refactor TruthTable to use Seq (#2217)

This makes the resulting Verilog from decoding a TruthTable deterministic.---
 .../src/test/scala/chiselTests/util/experimental/DecoderSpec.scala    | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'integration-tests/src/test/scala/chiselTests/util/experimental/DecoderSpec.scala')

diff --git a/integration-tests/src/test/scala/chiselTests/util/experimental/DecoderSpec.scala b/integration-tests/src/test/scala/chiselTests/util/experimental/DecoderSpec.scala
index c31fdee0..2d50555e 100644
--- a/integration-tests/src/test/scala/chiselTests/util/experimental/DecoderSpec.scala
+++ b/integration-tests/src/test/scala/chiselTests/util/experimental/DecoderSpec.scala
@@ -10,7 +10,7 @@ import chiseltest._
 import chiseltest.formal._
 
 class DecoderSpec extends AnyFlatSpec with ChiselScalatestTester with Formal  {
-  val xor = TruthTable(
+  val xor = TruthTable.fromString(
     """10->1
       |01->1
       |    0""".stripMargin)
@@ -42,7 +42,7 @@ class DecoderSpec extends AnyFlatSpec with ChiselScalatestTester with Formal  {
         """10->1
           |01->1
           |    0""".stripMargin,
-        QMCMinimizer.minimize(TruthTable(
+        QMCMinimizer.minimize(TruthTable.fromString(
           """10->1
             |01->1
             |    0""".stripMargin)).toString
-- 
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