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| author | Jack Koenig | 2021-01-21 20:31:39 -0800 |
|---|---|---|
| committer | GitHub | 2021-01-21 20:31:39 -0800 |
| commit | 53c24cb0a369d4c4f57c28c098b30e4d3640eac2 (patch) | |
| tree | 825776855e7d2fc28ef32ebb05df7339c24e00b3 /docs | |
| parent | 7e4d1eeb03fddff735e67e3fe36b6efbfac39711 (diff) | |
Apply suggestions from code review
Co-authored-by: Megan Wachs <megan@sifive.com>
Diffstat (limited to 'docs')
| -rw-r--r-- | docs/src/wiki-deprecated/ports.md | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/docs/src/wiki-deprecated/ports.md b/docs/src/wiki-deprecated/ports.md index e2b70050..251ce243 100644 --- a/docs/src/wiki-deprecated/ports.md +++ b/docs/src/wiki-deprecated/ports.md @@ -30,8 +30,7 @@ provide powerful wiring constructs described later. (Chisel 3.2+) -Chisel 3.2+ introduces an API `DataMirror.modulePorts` which can be used to inspect the IOs of any Chisel module, including Modules, RawModules, and BlackBoxes. - +Chisel 3.2 introduced `DataMirror.modulePorts` which can be used to inspect the IOs of any Chisel module (this includes modules in both `import chisel3._` and `import Chisel._`, as well as BlackBoxes from each package). Here is an example of how to use this API: ```scala |