summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
-rw-r--r--core/src/main/scala/chisel3/BlackBox.scala4
-rw-r--r--core/src/main/scala/chisel3/RawModule.scala4
-rw-r--r--docs/src/wiki-deprecated/ports.md3
3 files changed, 5 insertions, 6 deletions
diff --git a/core/src/main/scala/chisel3/BlackBox.scala b/core/src/main/scala/chisel3/BlackBox.scala
index 2aa9a243..03543790 100644
--- a/core/src/main/scala/chisel3/BlackBox.scala
+++ b/core/src/main/scala/chisel3/BlackBox.scala
@@ -146,10 +146,10 @@ abstract class BlackBox(val params: Map[String, Param] = Map.empty[String, Param
private[chisel3] override def generateComponent(): Component = {
_compatAutoWrapPorts() // pre-IO(...) compatibility hack
- // Restrict IO to just io, clock, and reset
+ // Restrict IO to just io, clock, and reset
require(_io != null, "BlackBox must have a port named 'io' of type Record!")
require(portsContains(_io), "BlackBox must have io wrapped in IO(...)")
- require(portsSize == 1, "BlackBox must only have io as IO")
+ require(portsSize == 1, "BlackBox must only have one IO, called `io`")
require(!_closed, "Can't generate module more than once")
_closed = true
diff --git a/core/src/main/scala/chisel3/RawModule.scala b/core/src/main/scala/chisel3/RawModule.scala
index a686fd7e..0adacedb 100644
--- a/core/src/main/scala/chisel3/RawModule.scala
+++ b/core/src/main/scala/chisel3/RawModule.scala
@@ -202,7 +202,7 @@ package object internal {
*/
abstract class LegacyModule(implicit moduleCompileOptions: CompileOptions) extends Module {
// Provide a non-deprecated constructor
- def this(override_clock: Option[Clock]=None, override_reset: Option[Bool]=None)
+ def this(override_clock: Option[Clock] = None, override_reset: Option[Bool]=None)
(implicit moduleCompileOptions: CompileOptions) = {
this()
this.override_clock = override_clock
@@ -243,7 +243,7 @@ package object internal {
/** Legacy BlackBox class will reflectively autowrap val io
*
- * '''Do not use this class in user code'''. Use whichever `Module` is imported by your wildcard
+ * '''Do not use this class in user code'''. Use whichever `BlackBox` is imported by your wildcard
* import (preferably `import chisel3._`).
*/
abstract class LegacyBlackBox(params: Map[String, Param] = Map.empty[String, Param])
diff --git a/docs/src/wiki-deprecated/ports.md b/docs/src/wiki-deprecated/ports.md
index e2b70050..251ce243 100644
--- a/docs/src/wiki-deprecated/ports.md
+++ b/docs/src/wiki-deprecated/ports.md
@@ -30,8 +30,7 @@ provide powerful wiring constructs described later.
(Chisel 3.2+)
-Chisel 3.2+ introduces an API `DataMirror.modulePorts` which can be used to inspect the IOs of any Chisel module, including Modules, RawModules, and BlackBoxes.
-
+Chisel 3.2 introduced `DataMirror.modulePorts` which can be used to inspect the IOs of any Chisel module (this includes modules in both `import chisel3._` and `import Chisel._`, as well as BlackBoxes from each package).
Here is an example of how to use this API:
```scala