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authorAdam Izraelevitz2020-10-26 16:48:44 -0700
committerGitHub2020-10-26 23:48:44 +0000
commit58fa3c1118d9e892895970d48e2ba8a3c182bb81 (patch)
treea672be8750c8c8dd2bb1645f88b4ce1bbbb37993 /docs/src/explanations/blackboxes.md
parent1b6bd89dfafc774af1c926a982418294091f6346 (diff)
Fix crosslinks in mdoc. Can't use md suffix (#1640)
* Fix crosslinks in mdoc. Can't use md suffix * Removed all .md crossrefs Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
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```
### Blackboxes with Verilog in a Resource File
-In order to deliver the verilog snippet above to the backend simulator, chisel3 provides the following tools based on the chisel/firrtl [annotation system](../explanations/annotations.md). Add the trait ```HasBlackBoxResource``` to the declaration, and then call a function in the body to say where the system can find the verilog. The Module now looks like
+In order to deliver the verilog snippet above to the backend simulator, chisel3 provides the following tools based on the chisel/firrtl [annotation system](../explanations/annotations). Add the trait ```HasBlackBoxResource``` to the declaration, and then call a function in the body to say where the system can find the verilog. The Module now looks like
```mdoc scala:silent:reset
class BlackBoxRealAdd extends BlackBox with HasBlackBoxResource {
val io = IO(new Bundle() {