diff options
| author | Adam Izraelevitz | 2020-10-26 16:48:44 -0700 |
|---|---|---|
| committer | GitHub | 2020-10-26 23:48:44 +0000 |
| commit | 58fa3c1118d9e892895970d48e2ba8a3c182bb81 (patch) | |
| tree | a672be8750c8c8dd2bb1645f88b4ce1bbbb37993 /docs/src/explanations | |
| parent | 1b6bd89dfafc774af1c926a982418294091f6346 (diff) | |
Fix crosslinks in mdoc. Can't use md suffix (#1640)
* Fix crosslinks in mdoc. Can't use md suffix
* Removed all .md crossrefs
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
Diffstat (limited to 'docs/src/explanations')
| -rw-r--r-- | docs/src/explanations/blackboxes.md | 2 | ||||
| -rw-r--r-- | docs/src/explanations/bundles-and-vecs.md | 2 | ||||
| -rw-r--r-- | docs/src/explanations/naming.md | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/docs/src/explanations/blackboxes.md b/docs/src/explanations/blackboxes.md index 7064c7bb..a8d5fe03 100644 --- a/docs/src/explanations/blackboxes.md +++ b/docs/src/explanations/blackboxes.md @@ -79,7 +79,7 @@ endmodule ``` ### Blackboxes with Verilog in a Resource File -In order to deliver the verilog snippet above to the backend simulator, chisel3 provides the following tools based on the chisel/firrtl [annotation system](../explanations/annotations.md). Add the trait ```HasBlackBoxResource``` to the declaration, and then call a function in the body to say where the system can find the verilog. The Module now looks like +In order to deliver the verilog snippet above to the backend simulator, chisel3 provides the following tools based on the chisel/firrtl [annotation system](../explanations/annotations). Add the trait ```HasBlackBoxResource``` to the declaration, and then call a function in the body to say where the system can find the verilog. The Module now looks like ```mdoc scala:silent:reset class BlackBoxRealAdd extends BlackBox with HasBlackBoxResource { val io = IO(new Bundle() { diff --git a/docs/src/explanations/bundles-and-vecs.md b/docs/src/explanations/bundles-and-vecs.md index 4b1eb196..0c8a77b3 100644 --- a/docs/src/explanations/bundles-and-vecs.md +++ b/docs/src/explanations/bundles-and-vecs.md @@ -77,7 +77,7 @@ Note that the builtin Chisel primitive and aggregate classes do not require the `new` when creating an instance, whereas new user datatypes will. A Scala `apply` constructor can be defined so that a user datatype also does not require `new`, as described in -[Function Constructor](../wiki-deprecated/functional-module-creation.md). +[Function Constructor](../wiki-deprecated/functional-module-creation). ### Flipping Bundles diff --git a/docs/src/explanations/naming.md b/docs/src/explanations/naming.md index 56c089bc..86db515c 100644 --- a/docs/src/explanations/naming.md +++ b/docs/src/explanations/naming.md @@ -12,7 +12,7 @@ they are declared. In addition, this release includes prolific use of a new pref naming of signals programmatically generated from function calls. This document explains how naming now works in Chisel for signal and module names. For cookbook examples on how to fix -systemic name-stability issues, please refer to the naming [cookbook](../cookbooks/naming.md). +systemic name-stability issues, please refer to the naming [cookbook](../cookbooks/naming). ### Compiler Plugin |
