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authorducky2016-05-20 18:09:57 -0700
committerducky2016-06-08 16:22:27 -0700
commitf36524e388b060b1bb535ae21cb1bcbbea220be9 (patch)
treea32772f816f18b14002948964917be0cb8280c48 /coreMacros
parent53813f61b7dfe246d214ab966739d01c65c8ecb0 (diff)
Rename packages to lowercase chisel, add compatibility layer
Diffstat (limited to 'coreMacros')
-rw-r--r--coreMacros/src/main/scala/chisel/internal/sourceinfo/SourceInfoTransform.scala (renamed from coreMacros/src/main/scala/Chisel/internal/sourceinfo/SourceInfoTransform.scala)4
1 files changed, 2 insertions, 2 deletions
diff --git a/coreMacros/src/main/scala/Chisel/internal/sourceinfo/SourceInfoTransform.scala b/coreMacros/src/main/scala/chisel/internal/sourceinfo/SourceInfoTransform.scala
index 82ad5b9e..10b677b6 100644
--- a/coreMacros/src/main/scala/Chisel/internal/sourceinfo/SourceInfoTransform.scala
+++ b/coreMacros/src/main/scala/chisel/internal/sourceinfo/SourceInfoTransform.scala
@@ -3,7 +3,7 @@
// This file transform macro definitions to explicitly add implicit source info to Chisel method
// calls.
-package Chisel.internal.sourceinfo
+package chisel.internal.sourceinfo
import scala.language.experimental.macros
import scala.reflect.macros.blackbox.Context
@@ -23,7 +23,7 @@ trait SourceInfoTransformMacro {
val c: Context
import c.universe._
def thisObj = c.prefix.tree
- def implicitSourceInfo = q"implicitly[_root_.Chisel.internal.sourceinfo.SourceInfo]"
+ def implicitSourceInfo = q"implicitly[_root_.chisel.internal.sourceinfo.SourceInfo]"
}
class WireTransform(val c: Context) extends SourceInfoTransformMacro {