Scala 2.13 support (#1751)

12 files changed, 61 insertions, 46 deletions

diff --git a/core/src/main/scala-2.12/scala/collection/immutable/package.scala b/core/src/main/scala-2.12/scala/collection/immutable/package.scala
new file mode 100644
index 00000000..7ae87d9b
--- /dev/null
+++ b/core/src/main/scala-2.12/scala/collection/immutable/package.scala
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: Apache-2.0
+
+package scala.collection
+
+import scala.collection.immutable.ListMap
+
+package object immutable {
+  val SeqMap = ListMap
+  type SeqMap[K, +V] = ListMap[K, V]
+
+  val VectorMap = ListMap
+  type VectorMap[K, +V] = ListMap[K, V]
+}
diff --git a/core/src/main/scala/chisel3/Aggregate.scala b/core/src/main/scala/chisel3/Aggregate.scala
index c0b965b6..0031e53b 100644
--- a/core/src/main/scala/chisel3/Aggregate.scala
+++ b/core/src/main/scala/chisel3/Aggregate.scala
@@ -4,7 +4,7 @@ package chisel3
 
 import chisel3.experimental.VecLiterals.AddVecLiteralConstructor
 
-import scala.collection.immutable.ListMap
+import scala.collection.immutable.{SeqMap, VectorMap}
 import scala.collection.mutable.{HashSet, LinkedHashMap}
 import scala.language.experimental.macros
 import chisel3.experimental.{BaseModule, BundleLiteralException, ChiselEnum, EnumType, VecLiteralException}
@@ -516,7 +516,7 @@ sealed class Vec[T <: Data] private[chisel3] (gen: => T, val length: Int)
       }
     }
 
-    clone.bind(VecLitBinding(ListMap(vecLitLinkedMap.toSeq:_*)))
+    clone.bind(VecLitBinding(VectorMap(vecLitLinkedMap.toSeq:_*)))
     clone
   }
 }
@@ -595,7 +595,7 @@ object VecInit extends SourceInfoDoc {
 /** A trait for [[Vec]]s containing common hardware generators for collection
   * operations.
   */
-trait VecLike[T <: Data] extends collection.IndexedSeq[T] with HasId with SourceInfoDoc {
+trait VecLike[T <: Data] extends IndexedSeq[T] with HasId with SourceInfoDoc {
   def apply(p: UInt): T = macro CompileOptionsTransform.pArg
 
   /** @group SourceInfoTransformMacro */
@@ -835,7 +835,7 @@ abstract class Record(private[chisel3] implicit val compileOptions: CompileOptio
     s"$className$bindingString"
   }
 
-  val elements: ListMap[String, Data]
+  def elements: SeqMap[String, Data]
 
   /** Name for Pretty Printing */
   def className: String = this.getClass.getSimpleName
@@ -958,7 +958,7 @@ abstract class Bundle(implicit compileOptions: CompileOptions) extends Record {
     *   assert(uint === "h12345678".U) // This will pass
     * }}}
     */
-  final lazy val elements: ListMap[String, Data] = {
+  final lazy val elements: SeqMap[String, Data] = {
     val nameMap = LinkedHashMap[String, Data]()
     for (m <- getPublicFields(classOf[Bundle])) {
       getBundleField(m) match {
@@ -985,7 +985,7 @@ abstract class Bundle(implicit compileOptions: CompileOptions) extends Record {
           }
       }
     }
-    ListMap(nameMap.toSeq sortWith { case ((an, a), (bn, b)) => (a._id > b._id) || ((a eq b) && (an > bn)) }: _*)
+    VectorMap(nameMap.toSeq sortWith { case ((an, a), (bn, b)) => (a._id > b._id) || ((a eq b) && (an > bn)) }: _*)
   }
 
   /**
diff --git a/core/src/main/scala/chisel3/Bits.scala b/core/src/main/scala/chisel3/Bits.scala
index 17829143..aa5b1abb 100644
--- a/core/src/main/scala/chisel3/Bits.scala
+++ b/core/src/main/scala/chisel3/Bits.scala
@@ -1147,6 +1147,7 @@ sealed class Bool() extends UInt(1.W) with Reset {
 package experimental {
 
   import chisel3.internal.firrtl.BinaryPoint
+  import chisel3.internal.requireIsHardware // Fix ambiguous import
 
   /** Chisel types that have binary points support retrieving
     * literal values as `Double` or `BigDecimal`
diff --git a/core/src/main/scala/chisel3/Data.scala b/core/src/main/scala/chisel3/Data.scala
index 0241f248..0832161e 100644
--- a/core/src/main/scala/chisel3/Data.scala
+++ b/core/src/main/scala/chisel3/Data.scala
@@ -122,6 +122,7 @@ object ActualDirection {
 }
 
 package experimental {
+  import chisel3.internal.requireIsHardware // Fix ambiguous import
 
   /** Experimental hardware construction reflection API
     */
@@ -763,35 +764,33 @@ object WireDefault {
   }
 }
 
-package internal {
-  /** RHS (source) for Invalidate API.
-    * Causes connection logic to emit a DefInvalid when connected to an output port (or wire).
-    */
-  private[chisel3] object InternalDontCare extends Element {
-    // This object should be initialized before we execute any user code that refers to it,
-    //  otherwise this "Chisel" object will end up on the UserModule's id list.
-    // We make it private to chisel3 so it has to be accessed through the package object.
+/** RHS (source) for Invalidate API.
+  * Causes connection logic to emit a DefInvalid when connected to an output port (or wire).
+  */
+final case object DontCare extends Element {
+  // This object should be initialized before we execute any user code that refers to it,
+  //  otherwise this "Chisel" object will end up on the UserModule's id list.
+  // We make it private to chisel3 so it has to be accessed through the package object.
 
-    private[chisel3] override val width: Width = UnknownWidth()
+  private[chisel3] override val width: Width = UnknownWidth()
 
-    bind(DontCareBinding(), SpecifiedDirection.Output)
-    override def cloneType: this.type = DontCare
+  bind(DontCareBinding(), SpecifiedDirection.Output)
+  override def cloneType: this.type = DontCare
 
-    override def toString: String = "DontCare()"
+  override def toString: String = "DontCare()"
 
-    override def litOption: Option[BigInt] = None
+  override def litOption: Option[BigInt] = None
 
-    def toPrintable: Printable = PString("DONTCARE")
+  def toPrintable: Printable = PString("DONTCARE")
 
-    private[chisel3] def connectFromBits(that: Bits)(implicit sourceInfo:  SourceInfo, compileOptions: CompileOptions): Unit = {
-      Builder.error("connectFromBits: DontCare cannot be a connection sink (LHS)")
-    }
+  private[chisel3] def connectFromBits(that: Bits)(implicit sourceInfo:  SourceInfo, compileOptions: CompileOptions): Unit = {
+    Builder.error("connectFromBits: DontCare cannot be a connection sink (LHS)")
+  }
 
-    def do_asUInt(implicit sourceInfo: chisel3.internal.sourceinfo.SourceInfo, compileOptions: CompileOptions): UInt = {
-      Builder.error("DontCare does not have a UInt representation")
-      0.U
-    }
-    // DontCare's only match themselves.
-    private[chisel3] def typeEquivalent(that: Data): Boolean = that == DontCare
+  def do_asUInt(implicit sourceInfo: chisel3.internal.sourceinfo.SourceInfo, compileOptions: CompileOptions): UInt = {
+    Builder.error("DontCare does not have a UInt representation")
+    0.U
   }
+  // DontCare's only match themselves.
+  private[chisel3] def typeEquivalent(that: Data): Boolean = that == DontCare
 }
diff --git a/core/src/main/scala/chisel3/Module.scala b/core/src/main/scala/chisel3/Module.scala
index ede9ccc6..b204be8d 100644
--- a/core/src/main/scala/chisel3/Module.scala
+++ b/core/src/main/scala/chisel3/Module.scala
@@ -4,9 +4,7 @@ package chisel3
 
 import scala.collection.immutable.ListMap
 import scala.collection.mutable.{ArrayBuffer, HashMap}
-import scala.collection.JavaConversions._
 import scala.language.experimental.macros
-import java.util.IdentityHashMap
 
 import chisel3.internal._
 import chisel3.internal.Builder._
@@ -139,6 +137,8 @@ abstract class Module(implicit moduleCompileOptions: CompileOptions) extends Raw
 
 package experimental {
 
+  import chisel3.internal.requireIsChiselType // Fix ambiguous import
+
   object IO {
     /** Constructs a port for the current Module
       *
diff --git a/core/src/main/scala/chisel3/Num.scala b/core/src/main/scala/chisel3/Num.scala
index e1af9bdb..70f2fbf0 100644
--- a/core/src/main/scala/chisel3/Num.scala
+++ b/core/src/main/scala/chisel3/Num.scala
@@ -226,7 +226,7 @@ trait NumObject {
     */
   def toBigInt(x: BigDecimal, binaryPoint: Int): BigInt = {
     val multiplier = math.pow(2, binaryPoint)
-    val result = (x * multiplier).rounded.toBigInt()
+    val result = (x * multiplier).rounded.toBigInt
     result
   }
 
diff --git a/core/src/main/scala/chisel3/RawModule.scala b/core/src/main/scala/chisel3/RawModule.scala
index d2ba6e84..f678c587 100644
--- a/core/src/main/scala/chisel3/RawModule.scala
+++ b/core/src/main/scala/chisel3/RawModule.scala
@@ -4,7 +4,6 @@ package chisel3
 
 import scala.collection.mutable.{ArrayBuffer, HashMap}
 import scala.util.Try
-import scala.collection.JavaConversions._
 import scala.language.experimental.macros
 
 import chisel3.experimental.BaseModule
diff --git a/core/src/main/scala/chisel3/internal/Binding.scala b/core/src/main/scala/chisel3/internal/Binding.scala
index 8a3c4330..300803ce 100644
--- a/core/src/main/scala/chisel3/internal/Binding.scala
+++ b/core/src/main/scala/chisel3/internal/Binding.scala
@@ -6,7 +6,7 @@ import chisel3._
 import chisel3.experimental.BaseModule
 import chisel3.internal.firrtl.LitArg
 
-import scala.collection.immutable.ListMap
+import scala.collection.immutable.VectorMap
 
 /** Requires that a node is hardware ("bound")
   */
@@ -126,4 +126,4 @@ case class ElementLitBinding(litArg: LitArg) extends LitBinding
 // Literal binding attached to the root of a Bundle, containing literal values of its children.
 case class BundleLitBinding(litMap: Map[Data, LitArg]) extends LitBinding
 // Literal binding attached to the root of a Vec, containing literal values of its children.
-case class VecLitBinding(litMap: ListMap[Data, LitArg]) extends LitBinding
+case class VecLitBinding(litMap: VectorMap[Data, LitArg]) extends LitBinding
diff --git a/core/src/main/scala/chisel3/internal/Builder.scala b/core/src/main/scala/chisel3/internal/Builder.scala
index 084bdc88..e1e4d460 100644
--- a/core/src/main/scala/chisel3/internal/Builder.scala
+++ b/core/src/main/scala/chisel3/internal/Builder.scala
@@ -655,7 +655,7 @@ private[chisel3] object Builder extends LazyLogging {
       errors.checkpoint()
       logger.warn("Done elaborating.")
 
-      (Circuit(components.last.name, components, annotations), mod)
+      (Circuit(components.last.name, components.toSeq, annotations.toSeq), mod)
     }
   }
   initializeSingletons()
diff --git a/core/src/main/scala/chisel3/internal/Error.scala b/core/src/main/scala/chisel3/internal/Error.scala
index 134f4c87..454be360 100644
--- a/core/src/main/scala/chisel3/internal/Error.scala
+++ b/core/src/main/scala/chisel3/internal/Error.scala
@@ -45,7 +45,7 @@ object ExceptionHelpers {
       }
 
       // Step 1: Remove elements from the top in the package trimlist
-      ((a: Array[StackTraceElement]) => a.view.dropWhile(inTrimlist))
+      ((a: Array[StackTraceElement]) => a.dropWhile(inTrimlist))
       // Step 2: Optionally remove elements from the bottom until the anchor
         .andThen(_.reverse)
         .andThen( a =>
@@ -125,10 +125,10 @@ class ChiselException(message: String, cause: Throwable = null) extends Exceptio
     }
 
     val trimmedLeft = throwable.getStackTrace().view.dropWhile(isBlacklisted)
-    val trimmedReverse = trimmedLeft.reverse
+    val trimmedReverse = trimmedLeft.toIndexedSeq.reverse.view
       .dropWhile(ste => !ste.getClassName.startsWith(builderName))
       .dropWhile(isBlacklisted)
-    trimmedReverse.reverse.toArray
+    trimmedReverse.toIndexedSeq.reverse.toArray
   }
 
   def chiselStackTrace: String = {
diff --git a/core/src/main/scala/chisel3/internal/Namer.scala b/core/src/main/scala/chisel3/internal/Namer.scala
index 1694d71d..c6e36cb6 100644
--- a/core/src/main/scala/chisel3/internal/Namer.scala
+++ b/core/src/main/scala/chisel3/internal/Namer.scala
@@ -8,9 +8,8 @@ import chisel3.experimental.NoChiselNamePrefix
 import scala.collection.mutable.Stack
 import scala.collection.mutable.ListBuffer
 
-import scala.collection.JavaConversions._
-
 import java.util.IdentityHashMap
+import scala.collection.JavaConverters._
 
 /** Recursive Function Namer overview
   *
@@ -81,7 +80,14 @@ class NamingContext extends NamingContextInterface {
   def addDescendant(ref: Any, descendant: NamingContext) {
     ref match {
       case ref: AnyRef =>
-        descendants.getOrElseUpdate(ref, ListBuffer[NamingContext]()) += descendant
+        // getOrElseUpdate
+        val l = descendants.get(ref)
+        val buf = if (l != null) l else {
+          val value = ListBuffer[NamingContext]()
+          descendants.put(ref, value)
+          value
+        }
+        buf += descendant
       case _ => anonymousDescendants += descendant
     }
   }
@@ -111,7 +117,7 @@ class NamingContext extends NamingContextInterface {
       }
     }
 
-    for (descendant <- descendants.values().flatten) {
+    for (descendant <- descendants.values.asScala.flatten) {
       // Where we have a broken naming link, just ignore the missing parts
       descendant.namePrefix(prefix)
     }
diff --git a/core/src/main/scala/chisel3/package.scala b/core/src/main/scala/chisel3/package.scala
index d5a4bfae..64cfa8b9 100644
--- a/core/src/main/scala/chisel3/package.scala
+++ b/core/src/main/scala/chisel3/package.scala
@@ -207,9 +207,6 @@ package object chisel3 {
     a.allElements
   }
   def getModulePorts(m: Module): Seq[Port] = m.getPorts
-  // Invalidate API - a DontCare element for explicit assignment to outputs,
-  //  indicating the signal is intentionally not driven.
-  val DontCare = chisel3.internal.InternalDontCare
 
   class BindingException(message: String) extends ChiselException(message)
   /** A function expected a Chisel type but got a hardware object