Get core to compile

20 files changed, 114 insertions, 135 deletions

diff --git a/core/src/main/scala/chisel3/Aggregate.scala b/core/src/main/scala/chisel3/Aggregate.scala
index 731d12de..fc9972aa 100644
--- a/core/src/main/scala/chisel3/Aggregate.scala
+++ b/core/src/main/scala/chisel3/Aggregate.scala
@@ -80,28 +80,6 @@ sealed abstract class Aggregate extends Data {
   }
 }
 
-object Vec {
-  /** Creates a new [[Vec]] with `n` entries of the specified data type.
-    *
-    * @note elements are NOT assigned by default and have no value
-    */
-  def apply[T <: Data](n: Int, gen: T): Vec[T] = {
-    new Vec(gen.cloneTypeFull, n)
-  }
-
-  /** Truncate an index to implement modulo-power-of-2 addressing. */
-  private[chisel3] def truncateIndex(
-    idx: UInt,
-    n:   BigInt
-  ): UInt = {
-    val w = (n - 1).bitLength
-    if (n <= 1) 0.U
-    else if (idx.width.known && idx.width.get <= w) idx
-    else if (idx.width.known) idx(w - 1, 0)
-    else (idx | 0.U(w.W))(w - 1, 0)
-  }
-}
-
 /** A vector (array) of [[Data]] elements. Provides hardware versions of various
   * collection transformation functions found in software array implementations.
   *
@@ -128,8 +106,9 @@ object Vec {
   *  - when multiple conflicting assignments are performed on a Vec element, the last one takes effect (unlike Mem, where the result is undefined)
   *  - Vecs, unlike classes in Scala's collection library, are propagated intact to FIRRTL as a vector type, which may make debugging easier
   */
-sealed class Vec[T <: Data] private[chisel3] (gen: => T, val length: Int) extends Aggregate with Iterator[T] {
-
+class Vec[T <: Data] private[chisel3] (gen: => T, val vec_length: Int) extends Aggregate with Iterator[T] {
+  def hasNext: Boolean = ???
+  def next(): T = ???
   override def toString: String = {
     topBindingOpt match {
       case Some(VecLitBinding(vecLitBinding)) =>
@@ -137,14 +116,14 @@ sealed class Vec[T <: Data] private[chisel3] (gen: => T, val length: Int) extend
           case ((data, lit), index) =>
             s"$index=$lit"
         }.mkString(", ")
-        s"${sample_element.cloneType}[$length]($contents)"
-      case _ => stringAccessor(s"${sample_element.cloneType}[$length]")
+        s"${sample_element.cloneType}[$vec_length]($contents)"
+      case _ => stringAccessor(s"${sample_element.cloneType}[$vec_length]")
     }
   }
 
   private[chisel3] override def typeEquivalent(that: Data): Boolean = that match {
     case that: Vec[T] =>
-      this.length == that.length &&
+      this.vec_length == that.vec_length &&
       (this.sample_element.typeEquivalent(that.sample_element))
     case _ => false
   }
@@ -168,7 +147,7 @@ sealed class Vec[T <: Data] private[chisel3] (gen: => T, val length: Int) extend
   // that all elements must be the same and because it makes FIRRTL generation
   // simpler.
   private lazy val self: Seq[T] = {
-    val _self = Vector.fill(length)(gen)
+    val _self = Vector.fill(vec_length)(gen)
     for ((elt, i) <- _self.zipWithIndex)
       elt.setRef(this, i)
     _self
@@ -437,12 +416,33 @@ sealed class Vec[T <: Data] private[chisel3] (gen: => T, val length: Int) extend
         }
     }
 
-    clone.bind(VecLitBinding(VectorMap(vecLitLinkedMap.toSeq: _*)))
-    clone
+    clone.bind(VecLitBinding(VectorMap(vecLitLinkedMap.toSeq*)))
+    clone.asInstanceOf[this.type]
   }
+
 }
 
-object VecInit {
+object Vec {
+
+  /** Creates a new [[Vec]] with `n` entries of the specified data type.
+    *
+    * @note elements are NOT assigned by default and have no value
+    */
+  def apply[T <: Data](n: Int, gen: T): Vec[T] = {
+    new Vec(gen.cloneTypeFull, n)
+  }
+
+  /** Truncate an index to implement modulo-power-of-2 addressing. */
+  private[chisel3] def truncateIndex(
+    idx: UInt,
+    n:   BigInt
+  ): UInt = {
+    val w = (n - 1).bitLength
+    if (n <= 1) 0.U
+    else if (idx.width.known && idx.width.get <= w) idx
+    else if (idx.width.known) idx(w - 1, 0)
+    else (idx | 0.U(w.W))(w - 1, 0)
+  }
 
   /** Gets the correct connect operation (directed hardware assign or bulk connect) for element in Vec.
     */
@@ -482,7 +482,7 @@ object VecInit {
     elts.foreach(requireIsHardware(_, "vec element"))
 
     val vec: Vec[T] = Wire(Vec(elts.length, cloneSupertype(elts, "Vec")))
-    val op = getConnectOpFromDirectionality(vec.head)
+    val op = getConnectOpFromDirectionality(vec(0))
 
     (vec.zip(elts)).foreach { x =>
       op(x._1, x._2)
@@ -538,7 +538,7 @@ object VecInit {
 
     val tpe = cloneSupertype(flatElts, "Vec.tabulate")
     val myVec = Wire(Vec(n, Vec(m, tpe)))
-    val op = getConnectOpFromDirectionality(myVec.head.head)
+    val op = getConnectOpFromDirectionality(myVec(0)(0))
     for {
       (xs1D, ys1D) <- myVec.zip(elts)
       (x, y) <- xs1D.zip(ys1D)
@@ -572,7 +572,7 @@ object VecInit {
 
     val tpe = cloneSupertype(flatElts, "Vec.tabulate")
     val myVec = Wire(Vec(n, Vec(m, Vec(p, tpe))))
-    val op = getConnectOpFromDirectionality(myVec.head.head.head)
+    val op = getConnectOpFromDirectionality(myVec(0)(0)(0))
 
     for {
       (xs2D, ys2D) <- myVec.zip(elts)
@@ -651,44 +651,44 @@ object VecInit {
   // def apply[T <: Data](p: UInt): T
 
   // IndexedSeq has its own hashCode/equals that we must not use
-  override def hashCode: Int = super[HasId].hashCode
-  override def equals(that: Any): Boolean = super[HasId].equals(that)
+  override def hashCode: Int = super.hashCode
+  override def equals(that: Any): Boolean = super.equals(that)
 
   /** Outputs true if p outputs true for every element.
     */
-  def forall[T <: Data](p: T => Bool): Bool =
-    (this.map(p)).fold(true.B)(_ && _)
+  // def forall[T <: Data](p: T => Bool): Bool =
+  //   (this.toSeq.map(p)).fold(true.B)(_ && _)
 
   /** Outputs true if p outputs true for at least one element.
     */
-  def exists(p: T => Bool): Bool =
-    (this.map(p)).fold(false.B)(_ || _)
+  // def exists[T <: Data](p: T => Bool): Bool =
+  //   (this.toSeq.map(p)).fold(false.B)(_ || _)
 
   /** Outputs true if the vector contains at least one element equal to x (using
     * the === operator).
     */
-  def contains(x: T): Bool =
-    this.exists(_ === x)
+  // def contains[T <: Data](x: T): Bool =
+  //   this.exists(_ === x)
 
   /** Outputs the number of elements for which p is true.
     */
-  def count(p: T => Bool): UInt =
-    SeqUtils.count(this.map(p))
+  // def count[T <: Data](p: T => Bool): UInt =
+  //   SeqUtils.count(this.toSeq.map(p))
 
   /** Helper function that appends an index (literal value) to each element,
     * useful for hardware generators which output an index.
     */
-  private def indexWhereHelper(p: T => Bool) = this.map(p).zip((0 until length).map(i => i.asUInt))
+  // private def indexWhereHelper(p: T => Bool) = this.map(p).zip((0 until length).map(i => i.asUInt))
 
   /** Outputs the index of the first element for which p outputs true.
     */
-  def indexWhere(p: T => Bool): UInt =
-    SeqUtils.priorityMux(indexWhereHelper(p))
+  // def indexWhere(p: T => Bool): UInt =
+  //   SeqUtils.priorityMux(indexWhereHelper(p))
 
   /** Outputs the index of the last element for which p outputs true.
     */
-  def lastIndexWhere(p: T => Bool): UInt =
-    SeqUtils.priorityMux(indexWhereHelper(p).reverse)
+  // def lastIndexWhere(p: T => Bool): UInt =
+  //   SeqUtils.priorityMux(indexWhereHelper(p).reverse)
 
   /** Outputs the index of the element for which p outputs true, assuming that
     * the there is exactly one such element.
@@ -700,8 +700,8 @@ object VecInit {
     * true is NOT checked (useful in cases where the condition doesn't always
     * hold, but the results are not used in those cases)
     */
-  def onlyIndexWhere(p: T => Bool): UInt =
-    SeqUtils.oneHotMux(indexWhereHelper(p))
+  // def onlyIndexWhere(p: T => Bool): UInt =
+  //   SeqUtils.oneHotMux(indexWhereHelper(p))
 }
 
 /** Base class for Aggregates based on key values pairs of String and Data
@@ -824,7 +824,7 @@ abstract class Record extends Aggregate {
     val cloneFields = getRecursiveFields(clone, "(bundle root)").toMap
 
     // Create the Bundle literal binding from litargs of arguments
-    val bundleLitMap = elems.map { fn => fn(clone) }.flatMap {
+    val bundleLitMap = elems.map { fn => fn(clone.asInstanceOf[this.type]) }.flatMap {
       case (field, value) =>
         val fieldName = cloneFields.getOrElse(
           field,
@@ -912,7 +912,7 @@ abstract class Record extends Aggregate {
       throw new BundleLiteralException(s"duplicate fields $duplicateNames in Bundle literal constructor")
     }
     clone.bind(BundleLitBinding(bundleLitMap.toMap))
-    clone
+    clone.asInstanceOf[this.type]
   }
 
   /** The collection of [[Data]]
@@ -1161,7 +1161,7 @@ abstract class Bundle extends Record with experimental.AutoCloneType {
       case _ => None
     }.sortWith {
       case ((an, a), (bn, b)) => (a._id > b._id) || ((a eq b) && (an > bn))
-    }: _*)
+    }*)
   }
 
   /* The old, reflective implementation of Bundle.elements
@@ -1200,7 +1200,7 @@ abstract class Bundle extends Record with experimental.AutoCloneType {
           }
       }
     }
-    VectorMap(nameMap.toSeq.sortWith { case ((an, a), (bn, b)) => (a._id > b._id) || ((a eq b) && (an > bn)) }: _*)
+    VectorMap(nameMap.toSeq.sortWith { case ((an, a), (bn, b)) => (a._id > b._id) || ((a eq b) && (an > bn)) }*)
   }
 
   /**
@@ -1242,7 +1242,7 @@ abstract class Bundle extends Record with experimental.AutoCloneType {
   override def cloneType: this.type = {
     val clone = _cloneTypeImpl.asInstanceOf[this.type]
     checkClone(clone)
-    clone
+    clone.asInstanceOf[this.type]
   }
 
   // This is overriden for binary compatibility reasons in 3.5
diff --git a/core/src/main/scala/chisel3/Annotation.scala b/core/src/main/scala/chisel3/Annotation.scala
index 0410e1df..f527182f 100644
--- a/core/src/main/scala/chisel3/Annotation.scala
+++ b/core/src/main/scala/chisel3/Annotation.scala
@@ -35,7 +35,7 @@ trait ChiselMultiAnnotation {
   * FIRRTL.
   */
 trait RunFirrtlTransform extends ChiselAnnotation {
-  def transformClass: Class[_ <: Transform]
+  def transformClass: Class[? <: Transform]
 }
 
 object annotate {
diff --git a/core/src/main/scala/chisel3/Bits.scala b/core/src/main/scala/chisel3/Bits.scala
index ca18f475..c1c4c388 100644
--- a/core/src/main/scala/chisel3/Bits.scala
+++ b/core/src/main/scala/chisel3/Bits.scala
@@ -553,7 +553,7 @@ sealed class UInt private[chisel3] (width: Width) extends Bits(width) with Num[U
     "Chisel 3.5"
   )
 
-  def unary_!(): Bool = this === 0.U(1.W)
+def unary_! : Bool = this === 0.U(1.W)
 
   override def <<(that: Int): UInt =
     binop(UInt(this.width + that), ShiftLeftOp, validateShiftAmount(that))
@@ -593,19 +593,19 @@ sealed class UInt private[chisel3] (width: Width) extends Bits(width) with Num[U
     case _                         => this(n - 1, 0) ## (this >> n)
   }
 
-  private def dynamicShift(
-    n:           UInt,
-    staticShift: (UInt, Int) => UInt
-  ): UInt =
-    n.asBools().zipWithIndex.foldLeft(this) {
-      case (in, (en, sh)) => Mux(en, staticShift(in, 1 << sh), in)
-    }
+  // private def dynamicShift(
+  //   n:           UInt,
+  //   staticShift: (UInt, Int) => UInt
+  // ): UInt =
+  //   n.asBools().zipWithIndex.foldLeft(this) {
+  //     case (in, (en, sh)) => Mux(en, staticShift(in, 1 << sh), in)
+  //   }
 
-  def rotateRight(n: UInt): UInt =
-    dynamicShift(n, _ rotateRight _)
+  // def rotateRight(n: UInt): UInt =
+  //   dynamicShift(n, _ rotateRight _)
 
-  def rotateLeft(n: UInt): UInt =
-    dynamicShift(n, _ rotateLeft _)
+  // def rotateLeft(n: UInt): UInt =
+  //   dynamicShift(n, _ rotateLeft _)
 
   /** Conditionally set or clear a bit
     *
@@ -705,9 +705,9 @@ sealed class SInt private[chisel3] (width: Width) extends Bits(width) with Num[S
     "Chisel 3.5"
   )
 
-  def unary_-(): SInt = 0.S - this
+  def unary_- : SInt = 0.S - this
 
-  def unary_-%(): SInt = 0.S -% this
+  def unary_-% : SInt = 0.S -% this
 
   /** add (default - no growth) operator */
   override def +(that: SInt): SInt =
@@ -913,7 +913,7 @@ final class ResetType(private[chisel3] val width: Width = Width(1)) extends Elem
   /** Not really supported */
   def toPrintable: Printable = PString("Reset")
 
-  override def do_asUInt: UInt = pushOp(
+  def asUInt: UInt = pushOp(
     DefPrim(UInt(this.width), AsUIntOp, ref)
   )
 
diff --git a/core/src/main/scala/chisel3/Data.scala b/core/src/main/scala/chisel3/Data.scala
index 6b514e21..73b8e8c8 100644
--- a/core/src/main/scala/chisel3/Data.scala
+++ b/core/src/main/scala/chisel3/Data.scala
@@ -602,8 +602,8 @@ abstract class Data extends HasId with NamedComponent {
   private[chisel3] def bulkConnect(
     that: Data
   ): Unit = {
-    requireIsHardware(this, s"data to be bulk-connected")
-    requireIsHardware(that, s"data to be bulk-connected")
+    // requireIsHardware(this, s"data to be bulk-connected")
+    // requireIsHardware(that, s"data to be bulk-connected")
       (this.topBinding, that.topBinding) match {
       case (_: ReadOnlyBinding, _: ReadOnlyBinding) => throwException(s"Both $this and $that are read-only")
       // DontCare cannot be a sink (LHS)
@@ -700,7 +700,6 @@ abstract class Data extends HasId with NamedComponent {
   }
 
   private[chisel3] def width: Width
-  private[chisel3] def legacyConnect(that: Data): Unit
 
   /** Internal API; Chisel users should look at chisel3.chiselTypeOf(...).
     *
@@ -720,7 +719,7 @@ abstract class Data extends HasId with NamedComponent {
     val clone = this.cloneType.asInstanceOf[this.type] // get a fresh object, without bindings
     // Only the top-level direction needs to be fixed up, cloneType should do the rest
     clone.specifiedDirection = specifiedDirection
-    clone
+    clone.asInstanceOf[this.type]
   }
 
   /** Connect this $coll to that $coll mono-directionally and element-wise.
@@ -1069,7 +1068,7 @@ final case object DontCare extends Element {
     Builder.error("connectFromBits: DontCare cannot be a connection sink (LHS)")
   }
 
-  def do_asUInt: UInt = {
+  def asUInt: UInt = {
     Builder.error("DontCare does not have a UInt representation")
     0.U
   }
diff --git a/core/src/main/scala/chisel3/Mem.scala b/core/src/main/scala/chisel3/Mem.scala
index 0d77aa92..4966a106 100644
--- a/core/src/main/scala/chisel3/Mem.scala
+++ b/core/src/main/scala/chisel3/Mem.scala
@@ -135,7 +135,7 @@ sealed abstract class MemBase[T <: Data](val t: T, val length: BigInt)
     data: T,
     mask: Seq[Bool]
   )(
-    implicit evidence: T <:< Vec[_]
+    implicit evidence: T <:< Vec[?]
   ): Unit =
     masked_write_impl(idx, data, mask, Builder.forcedClock, true)
 
@@ -156,7 +156,7 @@ sealed abstract class MemBase[T <: Data](val t: T, val length: BigInt)
     mask:  Seq[Bool],
     clock: Clock
   )(
-    implicit evidence: T <:< Vec[_]
+    implicit evidence: T <:< Vec[?]
   ): Unit =
     masked_write_impl(idx, data, mask, clock, false)
 
@@ -167,7 +167,7 @@ sealed abstract class MemBase[T <: Data](val t: T, val length: BigInt)
     clock: Clock,
     warn:  Boolean
   )(
-    implicit evidence: T <:< Vec[_],
+    implicit evidence: T <:< Vec[?],
   ): Unit = {
     val accessor = makePort(idx, MemPortDirection.WRITE, clock).asInstanceOf[Vec[Data]]
     val dataVec = data.asInstanceOf[Vec[Data]]
diff --git a/core/src/main/scala/chisel3/Module.scala b/core/src/main/scala/chisel3/Module.scala
index 2c9e8189..22dbcc6f 100644
--- a/core/src/main/scala/chisel3/Module.scala
+++ b/core/src/main/scala/chisel3/Module.scala
@@ -73,7 +73,7 @@ object Module {
     if (Builder.currentModule.isDefined && module._component.isDefined) {
       val component = module._component.get
       pushCommand(DefInstance(module, component.ports))
-      module.initializeInParent
+      module.initializeInParent()
     }
     module
   }
@@ -173,7 +173,7 @@ abstract class Module extends RawModule {
 
   private[chisel3] override def initializeInParent(): Unit = {
 
-    super.initializeInParent
+    super.initializeInParent()
     clock := _override_clock.getOrElse(Builder.forcedClock)
     reset := _override_reset.getOrElse(Builder.forcedReset)
   }
@@ -255,7 +255,7 @@ package experimental {
 
     /** Sets up this module in the parent context
       */
-    private[chisel3] def initializeInParent: Unit
+    private[chisel3] def initializeInParent(): Unit
 
     //
     // Chisel Internals
@@ -335,7 +335,7 @@ package experimental {
       *
       * Helper method.
       */
-    protected def nameIds(rootClass: Class[_]): HashMap[HasId, String] = {
+    protected def nameIds(rootClass: Class[?]): HashMap[HasId, String] = {
       val names = new HashMap[HasId, String]()
 
       def name(node: HasId, name: String) = {
diff --git a/core/src/main/scala/chisel3/Printable.scala b/core/src/main/scala/chisel3/Printable.scala
index 82054ee1..4afe2498 100644
--- a/core/src/main/scala/chisel3/Printable.scala
+++ b/core/src/main/scala/chisel3/Printable.scala
@@ -132,7 +132,7 @@ object Printable {
     // The literal \ needs to be escaped before sending to the custom cf interpolator.
 
     val bufEscapeBackSlash = buf.map(_.replace("\\", "\\\\"))
-    StringContext(bufEscapeBackSlash.toSeq: _*).cf(data: _*)
+    StringContext(bufEscapeBackSlash.toSeq*).cf(data*)
   }
 
   private[chisel3] def checkScope(message: Printable): Unit = {
diff --git a/core/src/main/scala/chisel3/Printf.scala b/core/src/main/scala/chisel3/Printf.scala
index 1e98ba0f..9fc0973e 100644
--- a/core/src/main/scala/chisel3/Printf.scala
+++ b/core/src/main/scala/chisel3/Printf.scala
@@ -34,7 +34,7 @@ object printf {
   }
 
   /** Named class for [[printf]]s. */
-  final class Printf private[chisel3] (val pable: Printable) // extends VerificationStatement
+  final class Printf private[chisel3] (val pable: Printable) extends NamedComponent// extends VerificationStatement
 
   /** Prints a message in simulation
     *
@@ -116,5 +116,5 @@ object printf {
     fmt:  String,
     data: Bits*
   ): Printf =
-    printfWithoutReset(Printable.pack(fmt, data: _*))
+    printfWithoutReset(Printable.pack(fmt, data*))
 }
diff --git a/core/src/main/scala/chisel3/RawModule.scala b/core/src/main/scala/chisel3/RawModule.scala
index 01e5f9f5..4e724b1b 100644
--- a/core/src/main/scala/chisel3/RawModule.scala
+++ b/core/src/main/scala/chisel3/RawModule.scala
@@ -114,7 +114,7 @@ abstract class RawModule extends BaseModule {
     _component
   }
 
-  private[chisel3] def initializeInParent: Unit = {}
+  private[chisel3] def initializeInParent(): Unit = {}
 }
 
 trait RequireAsyncReset extends Module {
diff --git a/core/src/main/scala/chisel3/When.scala b/core/src/main/scala/chisel3/When.scala
index 940ebd8f..2848d925 100644
--- a/core/src/main/scala/chisel3/When.scala
+++ b/core/src/main/scala/chisel3/When.scala
@@ -81,7 +81,7 @@ final class WhenContext private[chisel3] (
   /** Returns the local condition, inverted for an otherwise */
   private[chisel3] def localCond: Bool = {
     val alt = altConds.foldRight(true.B) {
-      case (c, acc) => acc & !(c())
+      case (c, acc) => acc & !c()
     }
     cond
       .map(alt && _())
diff --git a/core/src/main/scala/chisel3/experimental/Analog.scala b/core/src/main/scala/chisel3/experimental/Analog.scala
index c932228f..fec02e50 100644
--- a/core/src/main/scala/chisel3/experimental/Analog.scala
+++ b/core/src/main/scala/chisel3/experimental/Analog.scala
@@ -73,7 +73,7 @@ final class Analog private (private[chisel3] val width: Width) extends Element {
     binding = target
   }
 
-  override def do_asUInt: UInt =
+  override def asUInt: UInt =
     throwException("Analog does not support asUInt")
 
   private[chisel3] override def connectFromBits(
diff --git a/core/src/main/scala/chisel3/experimental/ChiselEnum.scala b/core/src/main/scala/chisel3/experimental/ChiselEnum.scala
index d8c3fe0b..9d69fe37 100644
--- a/core/src/main/scala/chisel3/experimental/ChiselEnum.scala
+++ b/core/src/main/scala/chisel3/experimental/ChiselEnum.scala
@@ -141,9 +141,9 @@ abstract class EnumType(private[chisel3] val factory: ChiselEnum, selfAnnotating
     * @param s a [[scala.collection.Seq$ Seq]] of enumeration values to look for
     * @return a hardware [[Bool]] that indicates if this value matches any of the given values
     */
-  final def isOneOf(s: Seq[EnumType]): Bool = {
-    VecInit(s.map(this === _)).asUInt().orR()
-  }
+  // final def isOneOf(s: Seq[EnumType]): Bool = {
+  //   Vec(s.map(this === _)).asUInt().orR()
+  // }
 
   /** Test if this enumeration is equal to any of the values given as arguments
     *
@@ -151,10 +151,10 @@ abstract class EnumType(private[chisel3] val factory: ChiselEnum, selfAnnotating
     * @param u2 zero or more additional values to look for
     * @return a hardware [[Bool]] that indicates if this value matches any of the given values
     */
-  final def isOneOf(
-    u1: EnumType,
-    u2: EnumType*
-  ): Bool = isOneOf(u1 +: u2.toSeq)
+  // final def isOneOf(
+  //   u1: EnumType,
+  //   u2: EnumType*
+  // ): Bool = isOneOf(u1 +: u2.toSeq)
 
   def next: this.type = {
     if (litOption.isDefined) {
@@ -204,7 +204,7 @@ abstract class EnumType(private[chisel3] val factory: ChiselEnum, selfAnnotating
       }.flatten.toSeq
   }
 
-  private def outerMostVec(d: Data = this): Option[Vec[_]] = {
+  private def outerMostVec(d: Data = this): Option[Vec[?]] = {
     val currentVecOpt = d match {
       case v: Vec[_] => Some(v)
       case _ => None
@@ -253,7 +253,7 @@ abstract class EnumType(private[chisel3] val factory: ChiselEnum, selfAnnotating
     for ((name, value) <- allNamesPadded) {
       when(this === value) {
         for ((r, c) <- result.zip(name)) {
-          r := c.toChar.U
+          r := c.toInt.U
         }
       }
     }
diff --git a/core/src/main/scala/chisel3/experimental/Trace.scala b/core/src/main/scala/chisel3/experimental/Trace.scala
index eb2ed46a..b3ac37f9 100644
--- a/core/src/main/scala/chisel3/experimental/Trace.scala
+++ b/core/src/main/scala/chisel3/experimental/Trace.scala
@@ -5,6 +5,7 @@ import chisel3.{Aggregate, Data, Element, Module, RawModule}
 import firrtl.AnnotationSeq
 import firrtl.annotations.{Annotation, CompleteTarget, SingleTargetAnnotation}
 import firrtl.transforms.DontTouchAllTargets
+import firrtl.annoSeqToSeq
 
 /** The util that records the reference map from original [[Data]]/[[Module]] annotated in Chisel and final FIRRTL.
   * @example
diff --git a/core/src/main/scala/chisel3/experimental/package.scala b/core/src/main/scala/chisel3/experimental/package.scala
index 4862e209..80c3e28a 100644
--- a/core/src/main/scala/chisel3/experimental/package.scala
+++ b/core/src/main/scala/chisel3/experimental/package.scala
@@ -123,7 +123,7 @@ package object experimental {
   object BundleLiterals {
     implicit class AddBundleLiteralConstructor[T <: Record](x: T) {
       def Lit(elems: (T => (Data, Data))*): T = {
-        x._makeLit(elems: _*)
+        x._makeLit(elems*)
       }
     }
   }
@@ -140,7 +140,7 @@ package object experimental {
         * @return
         */
       def Lit(elems: (Int, T)*): Vec[T] = {
-        x._makeLit(elems: _*)
+        x._makeLit(elems*)
       }
     }
 
@@ -154,7 +154,7 @@ package object experimental {
         val indexElements: Seq[(Int, T)] = elems.zipWithIndex.map { case (element, index) => (index, element) }
         val widestElement: T = elems.maxBy(_.getWidth)
         val vec: Vec[T] = Vec.apply(indexElements.length, chiselTypeOf(widestElement))
-        vec.Lit(indexElements: _*)
+        vec.Lit(indexElements*)
       }
     }
   }
diff --git a/core/src/main/scala/chisel3/internal/BiConnect.scala b/core/src/main/scala/chisel3/internal/BiConnect.scala
index 46a2c134..c45a97f9 100644
--- a/core/src/main/scala/chisel3/internal/BiConnect.scala
+++ b/core/src/main/scala/chisel3/internal/BiConnect.scala
@@ -367,9 +367,6 @@ private[chisel3] object BiConnect {
 
   // This function checks if analog element-level attaching is allowed, then marks the Analog as connected
   def markAnalogConnected(analog: Analog, contextModule: BaseModule): Unit = {
-    analog.biConnectLocs.get(contextModule) match {
-      case Some(sl) => throw AttachAlreadyBulkConnectedException
-      case None     => // Do nothing
-    }
+    println("not doing anything for analog till we have sourceinfos again")
   }
 }
diff --git a/core/src/main/scala/chisel3/internal/Builder.scala b/core/src/main/scala/chisel3/internal/Builder.scala
index 0a63bc74..d62f2934 100644
--- a/core/src/main/scala/chisel3/internal/Builder.scala
+++ b/core/src/main/scala/chisel3/internal/Builder.scala
@@ -355,9 +355,9 @@ private[chisel3] trait HasId extends InstanceId {
     case Some(p)          => p.circuitName
   }
 
-  private[chisel3] def getPublicFields(rootClass: Class[_]): Seq[java.lang.reflect.Method] = {
+  private[chisel3] def getPublicFields(rootClass: Class[?]): Seq[java.lang.reflect.Method] = {
     // Suggest names to nodes using runtime reflection
-    def getValNames(c: Class[_]): Set[String] = {
+    def getValNames(c: Class[?]): Set[String] = {
       if (c == rootClass) {
         Set()
       } else {
@@ -726,7 +726,7 @@ private[chisel3] object Builder extends LazyLogging {
   }
 
   def getScalaMajorVersion: Int = {
-    val "2" :: major :: _ :: Nil = chisel3.BuildInfo.scalaVersion.split("\\.").toList
+    val "2" :: major :: _ :: Nil = chisel3.BuildInfo.scalaVersion.split("\\.").toList: @unchecked
     major.toInt
   }
 
diff --git a/core/src/main/scala/chisel3/internal/Namer.scala b/core/src/main/scala/chisel3/internal/Namer.scala
index 45efa052..0deb0c55 100644
--- a/core/src/main/scala/chisel3/internal/Namer.scala
+++ b/core/src/main/scala/chisel3/internal/Namer.scala
@@ -53,7 +53,7 @@ sealed trait NamingContextInterface {
     * so that actual naming calls (HasId.suggestName) can happen.
     * Recursively names descendants, for those whose return value have an associated name.
     */
-  def namePrefix(prefix: String): String
+  def namePrefix(prefix: String): Unit
 }
 
 /** Dummy implementation to allow for naming annotations in a non-Builder context.
diff --git a/core/src/main/scala/chisel3/internal/firrtl/Converter.scala b/core/src/main/scala/chisel3/internal/firrtl/Converter.scala
index 3c4a01b2..08c96f48 100644
--- a/core/src/main/scala/chisel3/internal/firrtl/Converter.scala
+++ b/core/src/main/scala/chisel3/internal/firrtl/Converter.scala
@@ -96,7 +96,7 @@ private[chisel3] object Converter {
       val consts = e.args.collect { case ILit(i) => i }
       val args = e.args.flatMap {
         case _: ILit => None
-        case other => Some(convert(other, ctx, fir.NoInfo))
+        case other => Some(convert(other, ctx))
       }
       val expr = e.op.name match {
         case "mux" =>
@@ -168,24 +168,6 @@ private[chisel3] object Converter {
           e.name
         )
       )
-    case e @ Verification(_, op, clk, pred, msg) =>
-      val firOp = op match {
-        case Formal.Assert => fir.Formal.Assert
-        case Formal.Assume => fir.Formal.Assume
-        case Formal.Cover  => fir.Formal.Cover
-      }
-      None
-      // Some(
-      //   fir.Verification(
-      //     firOp,
-      //     fir.NoInfo,
-      //     convert(clk, ctx),
-      //     convert(pred, ctx),
-      //     firrtl.Utils.one,
-      //     fir.StringLit(msg),
-      //     e.name
-      //   )
-      // )
     case _ => None
   }
 
@@ -245,7 +227,7 @@ private[chisel3] object Converter {
                 else frame.when.copy(conseq = fir.Block(stmts.result()))
               // Check if this when has an else
               cmdsIt.headOption match {
-                case Some(AltBegin(_)) =>
+                case Some(AltBegin()) =>
                   assert(!frame.alt, "Internal Error! Unexpected when structure!") // Only 1 else per when
                   scope = frame.copy(when = when, alt = true) :: scope.tail
                   cmdsIt.next() // Consume the AltBegin
diff --git a/core/src/main/scala/chisel3/internal/firrtl/IR.scala b/core/src/main/scala/chisel3/internal/firrtl/IR.scala
index 6f993847..551b6138 100644
--- a/core/src/main/scala/chisel3/internal/firrtl/IR.scala
+++ b/core/src/main/scala/chisel3/internal/firrtl/IR.scala
@@ -365,10 +365,10 @@ case class Circuit(
     )
 
   def copy(
-    name:        String = name,
-    components:  Seq[Component] = components,
-    annotations: Seq[ChiselAnnotation] = annotations,
-    renames:     RenameMap = renames
+    name:        String,
+    components:  Seq[Component],
+    annotations: Seq[ChiselAnnotation],
+    renames:     RenameMap
   ) = Circuit(name, components, annotations, renames, newAnnotations)
 
 }
diff --git a/core/src/main/scala/chisel3/package.scala b/core/src/main/scala/chisel3/package.scala
index b417e421..856cbbd2 100644
--- a/core/src/main/scala/chisel3/package.scala
+++ b/core/src/main/scala/chisel3/package.scala
@@ -196,7 +196,7 @@ package object chisel3 {
     def p(args: Any*): Printable = {
       // P interpolator does not treat % differently - hence need to add % before sending to cf.
       val t = sc.parts.map(_.replaceAll("%", "%%"))
-      StringContext(t: _*).cf(args: _*)
+      StringContext(t*).cf(args*)
     }
 
     /** Custom string interpolator for generating formatted Printables : cf"..."