1 files changed, 3 insertions, 3 deletions
diff --git a/core/src/main/scala/chisel3/Mem.scala b/core/src/main/scala/chisel3/Mem.scala
index 0d77aa92..4966a106 100644
--- a/core/src/main/scala/chisel3/Mem.scala
+++ b/core/src/main/scala/chisel3/Mem.scala
@@ -135,7 +135,7 @@ sealed abstract class MemBase[T <: Data](val t: T, val length: BigInt)
     data: T,
     mask: Seq[Bool]
   )(
-    implicit evidence: T <:< Vec[_]
+    implicit evidence: T <:< Vec[?]
   ): Unit =
     masked_write_impl(idx, data, mask, Builder.forcedClock, true)
 
@@ -156,7 +156,7 @@ sealed abstract class MemBase[T <: Data](val t: T, val length: BigInt)
     mask:  Seq[Bool],
     clock: Clock
   )(
-    implicit evidence: T <:< Vec[_]
+    implicit evidence: T <:< Vec[?]
   ): Unit =
     masked_write_impl(idx, data, mask, clock, false)
 
@@ -167,7 +167,7 @@ sealed abstract class MemBase[T <: Data](val t: T, val length: BigInt)
     clock: Clock,
     warn:  Boolean
   )(
-    implicit evidence: T <:< Vec[_],
+    implicit evidence: T <:< Vec[?],
   ): Unit = {
     val accessor = makePort(idx, MemPortDirection.WRITE, clock).asInstanceOf[Vec[Data]]
     val dataVec = data.asInstanceOf[Vec[Data]]