diff options
| author | Jack Koenig | 2020-10-30 09:57:30 -0700 |
|---|---|---|
| committer | GitHub | 2020-10-30 09:57:30 -0700 |
| commit | 0979133b2e67c82f916c2739bbda5df1c692a1d3 (patch) | |
| tree | 1ef0ef42595a1e59fe9f545895589e9e92f29d17 /core/src | |
| parent | 362a3e3552cfe90d980e81cc6928abe25c06243d (diff) | |
Fix bug where refs may not get set for Records (#1645)
This requires a combination of things, but it happens to be a
combination used by Diplomacy in Rocket Chip. It must be a Record in
compatibility code with Vecs as fields and a mix of components with and
without set directions.
Diffstat (limited to 'core/src')
| -rw-r--r-- | core/src/main/scala/chisel3/Aggregate.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/core/src/main/scala/chisel3/Aggregate.scala b/core/src/main/scala/chisel3/Aggregate.scala index 6c11b2db..e45f5b46 100644 --- a/core/src/main/scala/chisel3/Aggregate.scala +++ b/core/src/main/scala/chisel3/Aggregate.scala @@ -493,7 +493,6 @@ abstract class Record(private[chisel3] implicit val compileOptions: CompileOptio private[chisel3] override def bind(target: Binding, parentDirection: SpecifiedDirection): Unit = { try { super.bind(target, parentDirection) - setElementRefs() } catch { // nasty compatibility mode shim, where anything flies case e: MixedDirectionAggregateException if !compileOptions.dontAssumeDirectionality => val resolvedDirection = SpecifiedDirection.fromParent(parentDirection, specifiedDirection) @@ -503,6 +502,7 @@ abstract class Record(private[chisel3] implicit val compileOptions: CompileOptio case _ => ActualDirection.Bidirectional(ActualDirection.Default) } } + setElementRefs() } /** Creates a Bundle literal of this type with specified values. this must be a chisel type. |