diff options
| author | Jack Koenig | 2021-07-09 14:29:45 -0700 |
|---|---|---|
| committer | GitHub | 2021-07-09 14:29:45 -0700 |
| commit | 5183ef888274c1d9cc2e22aef95c0e90d86e5122 (patch) | |
| tree | 2e96ec19c6ca814186b85502dd6f8ed0507e47fb /core/src/main | |
| parent | 4b7b771eeced366345779a75987ce552558a1c7e (diff) | |
Fix chisel3 <> for Bundles that contain compatibility Bundles (Take 2) (#2031)
PR #2023 fixed a composition issue for chisel3 biconnects delegating to
FIRRTL partial connect when compatibility mode Bundles are elements of
chisel3 Bundles. It missed an important case though that caused
previously working code to break.
The bug is fixed by doing the automatic flipping for compatibility mode
Bundles that have "Input" as a direction in addition to those that are
"Flipped".
Diffstat (limited to 'core/src/main')
| -rw-r--r-- | core/src/main/scala/chisel3/internal/BiConnect.scala | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/core/src/main/scala/chisel3/internal/BiConnect.scala b/core/src/main/scala/chisel3/internal/BiConnect.scala index fcea4fe2..aa7d7ac3 100644 --- a/core/src/main/scala/chisel3/internal/BiConnect.scala +++ b/core/src/main/scala/chisel3/internal/BiConnect.scala @@ -120,9 +120,10 @@ private[chisel3] object BiConnect { if (notStrict) { // chisel3 <> is commutative but FIRRTL <- is not val flipped = { + import ActualDirection._ // Everything is flipped when it's the port of a child val childPort = left_r._parent.get != context_mod - val isFlipped = left_r.direction == ActualDirection.Bidirectional(ActualDirection.Flipped) + val isFlipped = Seq(Bidirectional(Flipped), Input).contains(left_r.direction) isFlipped ^ childPort } val (newLeft, newRight) = if (flipped) pair.swap else pair |