diff options
| author | Jack Koenig | 2021-08-17 18:22:16 -0700 |
|---|---|---|
| committer | GitHub | 2021-08-18 01:22:16 +0000 |
| commit | 7c8a032e7e23902283035d93579b8dc477b32f6a (patch) | |
| tree | 1086c8ebb842500cec2b88b7c7a4d961dca8e964 /core/src/main/scala/chisel3/internal | |
| parent | e14bcb145860207a825f780e3d0984e869f605c9 (diff) | |
Revert "remove DefRegInit, change DefReg API with option definition. (#1944)" (#2080)
This reverts commit ed894c61474c8bc73761a6c360ef9d14505d853b.
Diffstat (limited to 'core/src/main/scala/chisel3/internal')
| -rw-r--r-- | core/src/main/scala/chisel3/internal/firrtl/Converter.scala | 4 | ||||
| -rw-r--r-- | core/src/main/scala/chisel3/internal/firrtl/IR.scala | 4 |
2 files changed, 4 insertions, 4 deletions
diff --git a/core/src/main/scala/chisel3/internal/firrtl/Converter.scala b/core/src/main/scala/chisel3/internal/firrtl/Converter.scala index e8fb197c..8efb2abc 100644 --- a/core/src/main/scala/chisel3/internal/firrtl/Converter.scala +++ b/core/src/main/scala/chisel3/internal/firrtl/Converter.scala @@ -117,10 +117,10 @@ private[chisel3] object Converter { Some(fir.DefNode(convert(e.sourceInfo), e.name, expr)) case e @ DefWire(info, id) => Some(fir.DefWire(convert(info), e.name, extractType(id, info))) - case e @ DefReg(info, id, clock, None) => + case e @ DefReg(info, id, clock) => Some(fir.DefRegister(convert(info), e.name, extractType(id, info), convert(clock, ctx, info), firrtl.Utils.zero, convert(getRef(id, info), ctx, info))) - case e @ DefReg(info, id, clock, Some(RegInitIR(reset, init))) => + case e @ DefRegInit(info, id, clock, reset, init) => Some(fir.DefRegister(convert(info), e.name, extractType(id, info), convert(clock, ctx, info), convert(reset, ctx, info), convert(init, ctx, info))) case e @ DefMemory(info, id, t, size) => diff --git a/core/src/main/scala/chisel3/internal/firrtl/IR.scala b/core/src/main/scala/chisel3/internal/firrtl/IR.scala index a45ae3c2..f8a3cf7f 100644 --- a/core/src/main/scala/chisel3/internal/firrtl/IR.scala +++ b/core/src/main/scala/chisel3/internal/firrtl/IR.scala @@ -758,8 +758,8 @@ abstract class Definition extends Command { case class DefPrim[T <: Data](sourceInfo: SourceInfo, id: T, op: PrimOp, args: Arg*) extends Definition case class DefInvalid(sourceInfo: SourceInfo, arg: Arg) extends Command case class DefWire(sourceInfo: SourceInfo, id: Data) extends Definition -case class RegInitIR(reset: Arg, init: Arg) -case class DefReg(sourceInfo: SourceInfo, id: Data, clock: Arg, regInit: Option[RegInitIR]) extends Definition +case class DefReg(sourceInfo: SourceInfo, id: Data, clock: Arg) extends Definition +case class DefRegInit(sourceInfo: SourceInfo, id: Data, clock: Arg, reset: Arg, init: Arg) extends Definition case class DefMemory(sourceInfo: SourceInfo, id: HasId, t: Data, size: BigInt) extends Definition case class DefSeqMemory(sourceInfo: SourceInfo, id: HasId, t: Data, size: BigInt, readUnderWrite: fir.ReadUnderWrite.Value) extends Definition case class DefMemPort[T <: Data](sourceInfo: SourceInfo, id: T, source: Node, dir: MemPortDirection, index: Arg, clock: Arg) extends Definition |