Get core to compile

2 files changed, 6 insertions, 24 deletions

diff --git a/core/src/main/scala/chisel3/internal/firrtl/Converter.scala b/core/src/main/scala/chisel3/internal/firrtl/Converter.scala
index 3c4a01b2..08c96f48 100644
--- a/core/src/main/scala/chisel3/internal/firrtl/Converter.scala
+++ b/core/src/main/scala/chisel3/internal/firrtl/Converter.scala
@@ -96,7 +96,7 @@ private[chisel3] object Converter {
       val consts = e.args.collect { case ILit(i) => i }
       val args = e.args.flatMap {
         case _: ILit => None
-        case other => Some(convert(other, ctx, fir.NoInfo))
+        case other => Some(convert(other, ctx))
       }
       val expr = e.op.name match {
         case "mux" =>
@@ -168,24 +168,6 @@ private[chisel3] object Converter {
           e.name
         )
       )
-    case e @ Verification(_, op, clk, pred, msg) =>
-      val firOp = op match {
-        case Formal.Assert => fir.Formal.Assert
-        case Formal.Assume => fir.Formal.Assume
-        case Formal.Cover  => fir.Formal.Cover
-      }
-      None
-      // Some(
-      //   fir.Verification(
-      //     firOp,
-      //     fir.NoInfo,
-      //     convert(clk, ctx),
-      //     convert(pred, ctx),
-      //     firrtl.Utils.one,
-      //     fir.StringLit(msg),
-      //     e.name
-      //   )
-      // )
     case _ => None
   }
 
@@ -245,7 +227,7 @@ private[chisel3] object Converter {
                 else frame.when.copy(conseq = fir.Block(stmts.result()))
               // Check if this when has an else
               cmdsIt.headOption match {
-                case Some(AltBegin(_)) =>
+                case Some(AltBegin()) =>
                   assert(!frame.alt, "Internal Error! Unexpected when structure!") // Only 1 else per when
                   scope = frame.copy(when = when, alt = true) :: scope.tail
                   cmdsIt.next() // Consume the AltBegin
diff --git a/core/src/main/scala/chisel3/internal/firrtl/IR.scala b/core/src/main/scala/chisel3/internal/firrtl/IR.scala
index 6f993847..551b6138 100644
--- a/core/src/main/scala/chisel3/internal/firrtl/IR.scala
+++ b/core/src/main/scala/chisel3/internal/firrtl/IR.scala
@@ -365,10 +365,10 @@ case class Circuit(
     )
 
   def copy(
-    name:        String = name,
-    components:  Seq[Component] = components,
-    annotations: Seq[ChiselAnnotation] = annotations,
-    renames:     RenameMap = renames
+    name:        String,
+    components:  Seq[Component],
+    annotations: Seq[ChiselAnnotation],
+    renames:     RenameMap
   ) = Circuit(name, components, annotations, renames, newAnnotations)
 
 }