Get core to compile

1 files changed, 1 insertions, 4 deletions

diff --git a/core/src/main/scala/chisel3/internal/BiConnect.scala b/core/src/main/scala/chisel3/internal/BiConnect.scala
index 46a2c134..c45a97f9 100644
--- a/core/src/main/scala/chisel3/internal/BiConnect.scala
+++ b/core/src/main/scala/chisel3/internal/BiConnect.scala
@@ -367,9 +367,6 @@ private[chisel3] object BiConnect {
 
   // This function checks if analog element-level attaching is allowed, then marks the Analog as connected
   def markAnalogConnected(analog: Analog, contextModule: BaseModule): Unit = {
-    analog.biConnectLocs.get(contextModule) match {
-      case Some(sl) => throw AttachAlreadyBulkConnectedException
-      case None     => // Do nothing
-    }
+    println("not doing anything for analog till we have sourceinfos again")
   }
 }