52 errors, removing implicit sourceinfo to clear more errors

1 files changed, 0 insertions, 21 deletions

diff --git a/core/src/main/scala/chisel3/SIntFactory.scala b/core/src/main/scala/chisel3/SIntFactory.scala
deleted file mode 100644
index 8cceda13..00000000
--- a/core/src/main/scala/chisel3/SIntFactory.scala
+++ /dev/null
@@ -1,21 +0,0 @@
-// SPDX-License-Identifier: Apache-2.0
-
-package chisel3
-
-import chisel3.internal.firrtl.{SLit, Width}
-
-trait SIntFactory {
-
-  /** Create an SInt type with inferred width. */
-  def apply(): SInt = apply(Width())
-
-  /** Create a SInt type or port with fixed width. */
-  def apply(width: Width): SInt = new SInt(width)
-
-  /** Create an SInt literal with specified width. */
-  protected[chisel3] def Lit(value: BigInt, width: Width): SInt = {
-    val lit = SLit(value, width)
-    val result = new SInt(lit.width)
-    lit.bindLitArg(result)
-  }
-}