diff options
| author | Jack Koenig | 2021-06-28 14:07:03 -0700 |
|---|---|---|
| committer | Jack Koenig | 2021-06-28 14:08:21 -0700 |
| commit | b87107ad41e948de9da9c349505de414b1a9db7f (patch) | |
| tree | c34ccf144e5ff3926a2e8a9316ff3444a3508f17 /core/src/main/scala/chisel3/RawModule.scala | |
| parent | d3e13ce24956871d2f0fd01ca3a7d89317e3db68 (diff) | |
Set refs for ModuleClone and ClonePorts in less hacky way
Diffstat (limited to 'core/src/main/scala/chisel3/RawModule.scala')
| -rw-r--r-- | core/src/main/scala/chisel3/RawModule.scala | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/core/src/main/scala/chisel3/RawModule.scala b/core/src/main/scala/chisel3/RawModule.scala index 5bcd4dbd..4a60ca47 100644 --- a/core/src/main/scala/chisel3/RawModule.scala +++ b/core/src/main/scala/chisel3/RawModule.scala @@ -7,6 +7,7 @@ import scala.util.Try import scala.language.experimental.macros import chisel3.experimental.{BaseModule, BaseSim} import chisel3.internal._ +import chisel3.internal.BaseModule.ModuleClone import chisel3.internal.Builder._ import chisel3.internal.firrtl._ import chisel3.internal.sourceinfo.UnlocatableSourceInfo @@ -74,6 +75,7 @@ abstract class RawModule(implicit moduleCompileOptions: CompileOptions) // All suggestions are in, force names to every node. for (id <- getIds) { id match { + case id: ModuleClone => id.setRefAndPortsRef(_namespace) // special handling case id: BaseModule => id.forceName(None, default=id.desiredName, _namespace) case id: MemBase[_] => id.forceName(None, default="MEM", _namespace) case id: BaseSim => id.forceName(None, default="SIM", _namespace) |