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authorJack Koenig2021-06-23 17:11:22 -0700
committerJack Koenig2021-06-28 14:08:21 -0700
commitd3e13ce24956871d2f0fd01ca3a7d89317e3db68 (patch)
tree9db523d08e6725d78421ab84624facf5a5258093 /core/src/main/scala/chisel3/RawModule.scala
parent6a806918b15d78613638c8d860538adbef9425b1 (diff)
Fix CloneModuleAsRecord support for .toTarget
Diffstat (limited to 'core/src/main/scala/chisel3/RawModule.scala')
-rw-r--r--core/src/main/scala/chisel3/RawModule.scala6
1 files changed, 3 insertions, 3 deletions
diff --git a/core/src/main/scala/chisel3/RawModule.scala b/core/src/main/scala/chisel3/RawModule.scala
index de93e781..5bcd4dbd 100644
--- a/core/src/main/scala/chisel3/RawModule.scala
+++ b/core/src/main/scala/chisel3/RawModule.scala
@@ -57,7 +57,7 @@ abstract class RawModule(implicit moduleCompileOptions: CompileOptions)
}
- private[chisel3] override def generateComponent(): Component = {
+ private[chisel3] override def generateComponent(): Option[Component] = {
require(!_closed, "Can't generate module more than once")
_closed = true
@@ -130,7 +130,7 @@ abstract class RawModule(implicit moduleCompileOptions: CompileOptions)
}
val component = DefModule(this, name, firrtlPorts, invalidateCommands ++ getCommands)
_component = Some(component)
- component
+ _component
}
private[chisel3] def initializeInParent(parentCompileOptions: CompileOptions): Unit = {
@@ -221,7 +221,7 @@ package object internal {
// Allow access to bindings from the compatibility package
protected def _compatIoPortBound() = portsContains(_io)
- private[chisel3] override def generateComponent(): Component = {
+ private[chisel3] override def generateComponent(): Option[Component] = {
_compatAutoWrapPorts() // pre-IO(...) compatibility hack
// Restrict IO to just io, clock, and reset