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| author | Aditya Naik | 2024-06-05 13:09:47 -0700 |
|---|---|---|
| committer | Aditya Naik | 2024-06-05 13:09:47 -0700 |
| commit | e9d996e2a4f27e194ce3503d3ea8d9651b3ac3c2 (patch) | |
| tree | 6e3cfbabc9b4542356843b8512946b4a0f8efde3 /core/src/main/scala/chisel3/Data.scala | |
| parent | c60561c8e7c58939e53b5a955f646900139d9c67 (diff) | |
Readd ports that were deleted for testing
Diffstat (limited to 'core/src/main/scala/chisel3/Data.scala')
| -rw-r--r-- | core/src/main/scala/chisel3/Data.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/core/src/main/scala/chisel3/Data.scala b/core/src/main/scala/chisel3/Data.scala index 73b8e8c8..1a7a0244 100644 --- a/core/src/main/scala/chisel3/Data.scala +++ b/core/src/main/scala/chisel3/Data.scala @@ -211,7 +211,7 @@ package experimental { * // ) * }}} */ - def modulePorts(target: BaseModule): Seq[(String, Data)] = Seq.empty + def modulePorts(target: BaseModule): Seq[(String, Data)] = target.getChiselPorts /** Returns a recursive representation of a module's ports with underscore-qualified names * {{{ |