summaryrefslogtreecommitdiff
path: root/chiselFrontend
diff options
context:
space:
mode:
authorducky2018-05-11 15:50:24 -0700
committerRichard Lin2018-07-04 18:39:28 -0500
commit9a551fe1cc9c15d1ab9fca204ec3bdac2f920c48 (patch)
tree727a3cb33eb61077e78707e4a28f959865388a3d /chiselFrontend
parent0d157633104cdd96b881726802c7691783aeb7e6 (diff)
still broken
Diffstat (limited to 'chiselFrontend')
-rw-r--r--chiselFrontend/src/main/scala/chisel3/internal/Builder.scala4
1 files changed, 2 insertions, 2 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
index fd228a8d..d6c3c5d6 100644
--- a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
@@ -299,7 +299,7 @@ private[chisel3] object Builder {
}
def build[T <: UserModule](f: => T): Circuit = {
- //chiselContext.withValue(new ChiselContext) {
+ chiselContext.withValue(new ChiselContext) {
dynamicContextVar.withValue(Some(new DynamicContext())) {
errors.info("Elaborating design...")
val mod = f
@@ -309,7 +309,7 @@ private[chisel3] object Builder {
Circuit(components.last.name, components, annotations)
}
- //}
+ }
}
initializeSingletons()
}