diff options
| author | Richard Lin | 2016-11-29 16:37:13 -0800 |
|---|---|---|
| committer | GitHub | 2016-11-29 16:37:13 -0800 |
| commit | 7680363982b02f53e9f76f5d5e242e44f17da6f7 (patch) | |
| tree | 1b68e829fa8503440fcc564ea8d26207b7e2fb88 /chiselFrontend | |
| parent | edb19a0559686a471141c74438f677c1e217a298 (diff) | |
Add feature warnings to build, fix feature warnings, fix some documentation (#387)
Diffstat (limited to 'chiselFrontend')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala index 17354799..9bbf9d0e 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala @@ -225,7 +225,7 @@ sealed class Vec[T <: Data] private (gen: => T, val length: Int) private[chisel3] lazy val flatten: IndexedSeq[Bits] = (0 until length).flatMap(i => this.apply(i).flatten) - for ((elt, i) <- self zipWithIndex) + for ((elt, i) <- self.zipWithIndex) elt.setRef(this, i) /** Default "pretty-print" implementation |
