diff options
| author | Jim Lawson | 2016-12-01 17:34:39 -0800 |
|---|---|---|
| committer | Andrew Waterman | 2016-12-01 17:34:39 -0800 |
| commit | 6725dbd501e3d3a0d6a626f69473115069ac3b34 (patch) | |
| tree | 1c0d8877f4c63c38f82303c71bdda1b87e65ace8 /chiselFrontend | |
| parent | 7680363982b02f53e9f76f5d5e242e44f17da6f7 (diff) | |
Fix spelling of "specified". (#392)
Diffstat (limited to 'chiselFrontend')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala index 262b939f..699cc13c 100644 --- a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala +++ b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala @@ -64,7 +64,7 @@ abstract class LitArg(val num: BigInt, widthArg: Width) extends Arg { protected def minWidth: Int if (forcedWidth) { require(widthArg.get >= minWidth, - s"The literal value ${num} was elaborated with a specificed width of ${widthArg.get} bits, but at least ${minWidth} bits are required.") + s"The literal value ${num} was elaborated with a specified width of ${widthArg.get} bits, but at least ${minWidth} bits are required.") } } |
