diff options
| author | Jack Koenig | 2018-07-02 15:27:13 -0700 |
|---|---|---|
| committer | GitHub | 2018-07-02 15:27:13 -0700 |
| commit | 3d8064a9f2fd49bffb402b91131087c19ca7d6fc (patch) | |
| tree | b72fe3f4579d99975b46f6687aabf65d9d8645bd /chiselFrontend | |
| parent | b17998eacb8e7b38b90829279e852bf8d5911f83 (diff) | |
Direct to FIRRTL (#829)
Provide direct conversion from ChiselIR to FIRRTL.
Provide Driver support for dumping ProtoBuf.
Diffstat (limited to 'chiselFrontend')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/Printable.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Printable.scala b/chiselFrontend/src/main/scala/chisel3/core/Printable.scala index 8c35c33a..7b3d8d4f 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Printable.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Printable.scala @@ -128,7 +128,7 @@ case class PString(str: String) extends Printable { (str replaceAll ("%", "%%"), List.empty) } /** Superclass for Firrtl format specifiers for Bits */ -sealed abstract class FirrtlFormat(specifier: Char) extends Printable { +sealed abstract class FirrtlFormat(private[chisel3] val specifier: Char) extends Printable { def bits: Bits def unpack(ctx: Component): (String, Iterable[String]) = { (s"%$specifier", List(bits.ref.fullName(ctx))) |